Hung Quoc Vuong, 60San Diego, CA

2020040, Dec 24, 2020

Sep 3, 2020

17/011720

- San Diego CA, US
Todd Christopher Reynolds - Santee CA, US
Hung Vuong - Carlsbad CA, US

G06F 3/06
G11C 5/14
G06F 1/3234
G11C 16/30
G06F 13/16

Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

2019027, Sep 5, 2019

Feb 27, 2019

16/287393

- San Diego CA, US
Hung VUONG - Carlsbad CA, US

G06F 3/06
G06F 11/30

Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response to a determination of a data fragmentation status of the flash memory device exceeding a threshold. The method includes determining a data fragmentation status of the flash memory device exceeding a threshold and requesting, by a host, the flash memory device to fragment data stored in the flash memory device in response to the determining the data fragmentation status exceeding the threshold.

2019006, Feb 28, 2019

Oct 30, 2018

16/175745

- San Diego CA, US
Robert HARDACKER - Fallbrook CA, US
Hung VUONG - Carlsbad CA, US

G11C 16/34
G06F 12/02

Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

2019003, Jan 31, 2019

Jul 9, 2018

16/030841

- San Diego CA, US
Todd Christopher REYNOLDS - Santee CA, US
Hung VUONG - Carlsbad CA, US

G06F 3/06
G06F 13/16

Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

2018013, May 17, 2018

Oct 12, 2017

15/782833

- San Diego CA, US
David TEB - Haifa, IL
Hung VUONG - Carlsbad CA, US
Venkatakrishnan GOPALAKRISHNAN - San Diego CA, US

G11C 7/10
G06F 12/02
G06F 3/06
G06F 13/16

In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

2018010, Apr 19, 2018

Oct 13, 2016

15/292675

- San Diego CA, US
David TEB - Haifa, IL
Hung VUONG - Carlsbad CA, US

G06F 3/06

Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.

2017036, Dec 21, 2017

Jun 6, 2017

15/615827

- San Diego CA, US
Robert HARDACKER - Fallbrook CA, US
Hung VUONG - Carlsbad CA, US

G11C 16/34
G06F 12/02

Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

2016037, Dec 29, 2016

Sep 9, 2016

15/260355

- San Diego CA, US
Nam Van Dang - San Diego CA, US
Hung Quoc Vuong - San Diego CA, US
Xiaohua Kong - San Diego CA, US

G06F 1/32
G06F 11/30
G06F 11/22
G06F 13/40

An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.