Ian H Field, 50832 Carmel Ave, Los Altos, CA 94022

7080178, Jul 18, 2006

Feb 9, 2004

10/773452

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G06F 13/24
G06F 13/26

710264, 710263

A data processing system nested interrupt controller responsive to priority level values associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

7124261, Oct 17, 2006

Feb 9, 2004

10/773453

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G06F 12/08

711155, 711202

A data processing system has a base data address region and a bit-band data address region. Memory accesses to the bit-band data address region are converted into memory accesses to the base data address region. In the process of this conversion specific bits within the base data address region are picked out for access whether that be via a read-modify-write operation or a masked read operation as appropriate. In this way, bit access is provided to data values within the base data address region by addressing specific address locations within the bit-band data address region.

7152186, Dec 19, 2006

Aug 4, 2003

10/633363

Cédric Airaud - Antibes, FR
Nicholas Esca Smith - Cambridger, GB
Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US
Man Cheung Joseph Yiu - Maidenhead, GB
David Francis McHale - Harrow, GB
Andrew Brookfield Swaine - Cambridge, GB

ARM Limited - Cambridge

G06F 11/00

714 30, 714 25, 714 31, 714733, 714734

A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

7197680, Mar 27, 2007

Apr 17, 2003

10/417330

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G01R 31/28

714724

An integrated circuit including diagnostic circuitry having serial scan chains or debug bus access circuits for establishing communication using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals. The serial protocol provides for a pacing signal for indicating to the external diagnostic device when it is ready to receive more data and/or when it has completed a particular diagnostic operation. This provides a self-pacing ability. A training signal generated by the external diagnostic device is detected by the interface circuit on initialization and used to derive sampling point timings.

7206884, Apr 17, 2007

Feb 11, 2004

10/775334

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US
Richard Roy Grisenthwaite - Cambridge, GB

Arm Limited - Cambridge

G06F 13/26

710265, 710262, 712244

A data processing system having a nested interrupt controller supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.

7243206, Jul 10, 2007

Apr 14, 2003

10/412693

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G06F 12/12

711202, 711209

A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data item and different to said at least one data item in a portion of a RAM memory block, said RAM memory block being accessible by said processor, and said portion having been defined for storage of said at least one replacement data item; intercepting a data access request from said processor to said ROM; comparing at least a portion of an address of said intercepted data access request with a stored at least one identifier, said stored at least one identifier identifying an address of at least one data item stored on said ROM, and depending on said comparison either: remapping said data access request to said RAM memory block, such that a replacement data item stored on said memory block is accessed if said comparison indicates said at least a portion of an address to correspond to an address identified by said at least one identifier; or if said comparison indicates said at least a portion of an address not to be an address identified by said at least one stored identifier accessing a data item located at a position corresponding to said address on said ROM.

7278073, Oct 2, 2007

Apr 17, 2003

10/417329

Paul Kimelman - Alamo CA, US
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G01R 31/28

714724

An integrated circuit is provided with a diagnostic data capture and output system in the form of a diagnostic data capture circuit which captures a data word and a context word from a bus. The bus may be the functional bus connecting functional circuits within the integrated circuit or a dedicated bus linking one or more functional circuits directly to the diagnostic data capture circuit. The diagnostic data captured is buffered within a first-in-first-out buffer and then serialised for output. The diagnostic data fields also include a time value indicative of the time at which the diagnostic data field concerned was captured and whether any diagnostic data fields have failed to be captured.

7412633, Aug 12, 2008

Jan 31, 2006

11/343210

Paul Kimelman - Alamo CA, US
Edmond John Simon Ashfield - Cambridge, GB
Thomas Sean Houlihane - Bassingbourn, GB
Ian Field - Walnut Creek CA, US

ARM Limited - Cambridge

G01R 31/28

714724

An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.