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Jiang Y HuNew York, NY

Jiang Hu Phones & Addresses

New York, NY   

Bronx, NY   

Brooklyn, NY   

Rockaway, NJ   

711 W 171St St, New York, NY 10032    212-7818286   

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Position: Precision Production Occupations

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Degree: Graduate or professional degree

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Jiang Hu Photo 30

Jiang Hu

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Jiang Hu Photo 31

Jiang Hu (Film)

Jiang Hu () (aka Gong Wu, Blood Brothers) is a 2004 Hong Kong film about ...

Us Patents

Integrated Circuit Buffering Solutions Considering Sink Delays

US Patent:
2019027, Sep 12, 2019
Filed:
May 28, 2019
Appl. No.:
16/423242
Inventors:
- Armonk NY, US
Stephen T. Quay - Vancouver, CA
Lakshmi N. Reddy - Mount Kisco NY, US
Gustavo E. Tellez - Essex Junction VT, US
Gi-Joon Nam - Chappaqua NY, US
Jiang Hu - College Station TX, US
International Classification:
G06F 17/50
Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Integrated Circuit Buffering Solutions Considering Sink Delays

US Patent:
2019027, Sep 12, 2019
Filed:
May 28, 2019
Appl. No.:
16/423391
Inventors:
- Armonk NY, US
Stephen T. Quay - Vancouver, CA
Lakshmi N. Reddy - Mount Kisco NY, US
Gustavo E. Tellez - Essex Junction VT, US
Gi-Joon Nam - Chappaqua NY, US
Jiang Hu - College Station TX, US
International Classification:
G06F 17/50
Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Light Fixture With Airflow Passage Separating Driver And Emitter

US Patent:
2018008, Mar 22, 2018
Filed:
Nov 29, 2017
Appl. No.:
15/825270
Inventors:
- Northvale NJ, US
Jiang Hu - Northvale NJ, US
Wengang Gao - Northvale NJ, US
International Classification:
F21V 29/76
F21V 29/83
Abstract:
An illustrative light fixture provides an emitter housing and a driver housing in a single fixture with an airflow channel defined between the emitter and driver housings. The airflow channel minimizes thermal conduction between the emitter and driver housings, and maximizes thermal convective cooling for at least one of the emitter housing and driver housing. The emitter housing includes vertical fins extending into the airflow chamber. The left and right sides of the emitter and driver housings define top and bottom edges that are respectively coplanar with the top and bottom edges of the vertical fins.

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