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Isaac M Wong, 45Union City, CA

Isaac Wong Phones & Addresses

Union City, CA   

Eugene, OR   

405 Rancho Arroyo Pkwy, Fremont, CA 94536   

Daly City, CA   

Santa Clara, CA   

Pacifica, CA   

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Isaac Wong resumes & CV records

Resumes

Isaac Wong Photo 28

Undergraduate Researcher

Location:
Pittsburgh, PA
Industry:
Biotechnology
Work:
Epic Jan 2018 - Jul 2018
Technical Services
Singapore Armed Forces (Saf) May 2017 - Jun 2017
Military Police Specialist
University of Pittsburgh May 2015 - Aug 2015
Student Researcher, Robertson Laboratory
Robertson Research Lab May 2015 - Aug 2015
Undergraduate Researcher
Singapore Armed Forces (Saf) Sep 2011 - Aug 2013
Access Control Force Commander
Education:
University of Pittsburgh 2013 - 2017
Bachelors, Bioengineering
University of Pittsburgh Swanson School of Engineering 2013 - 2017
Bachelors, Bioengineering
Winston Churchill High School 2008 - 2011
Skills:
Matlab, C++, Military, Microsoft Office, Analysis, Java, Solidworks, Html, Javascript, Css, Node.js
Languages:
English
Mandarin
Isaac Wong Photo 29

Graduate Teaching Assistant

Location:
Eugene, OR
Industry:
Biotechnology
Work:
Honeywell May 2019 - Aug 2019
R and D Software Engineering Intern
Georgia Institute of Technology May 2019 - Aug 2019
Graduate Teaching Assistant
Singapore Armed Forces May 2017 - Jun 2017
Military Police Specialist
University of Pittsburgh Jan 2016 - Apr 2017
Student Researcher at Zhou Laboratory
University of Pittsburgh May 2015 - Aug 2015
Student Researcher at Robertson Laboratory
Singapore Armed Forces Sep 2011 - Aug 2013
Access Control Force Commander
Education:
Georgia Institute of Technology 2018 - 2020
Master of Science, Masters
Skills:
Matlab, Java, Solidworks, C++, Analysis, Microsoft Office, Military, Html, Javascript, Css, Node.js
Isaac Wong Photo 30

Isaac Wong

Isaac Wong Photo 31

Computer Networking Professional

Location:
San Francisco Bay Area
Industry:
Computer Networking

Publications & IP owners

Us Patents

Digital To Analog Converter (Dac) Having An Adjustable Dynamic Range

US Patent:
6462689, Oct 8, 2002
Filed:
Jan 25, 2001
Appl. No.:
09/771397
Inventors:
Isaac H. Wong - Fremont CA
Assignee:
Ishoni Networks, Inc. - Santa Clara CA
International Classification:
H03M 166
US Classification:
341144, 341139, 341143, 341152
Abstract:
A digital to analog converter (DAC) has an adjustable dynamic range. Specifically, the adjustable DAC has a control port that receives a control signal indicative of the dynamic range, and the DAC produces an analog signal of the specified dynamic range in response to a corresponding digital signal. In one embodiment, the adjustable DAC includes a bitstream generator that repeatedly generates a bitstream and a low pass filter that receives and filters the repeated bitstream. The bitstream generator is adjustable, and can produce bitstreams of different lengths, depending on the control signal. Increasing the bitstream length results in a greater dynamic range of the analog signal, and vice versa. A user can use a preexisting filter to perform the low pass filtering, by simply selecting a value of the control signal. Alternatively, the user can set a value of the control signal (based on an applications dynamic range requirement), and design the low pass filter based on the selected value of the control signal.

Method And System For Maintaining Connections In A Network

US Patent:
2002010, Aug 8, 2002
Filed:
Feb 6, 2001
Appl. No.:
09/777609
Inventors:
Jacques Baudot - St-Vincent-de-Mercuze, FR
Stella Kwong - Los Altos CA, US
Isaac Wong - San Jose CA, US
Denis Roger - Varces, FR
Abdessattar Sassi - Cupertino CA, US
Marc Brandt - Eybens, FR
International Classification:
G06F015/16
H04L001/22
H04B001/74
H02H003/05
H05K010/00
H03K019/003
US Classification:
709/227000, 714/011000
Abstract:
The present invention provides a method for hosting a series of active connections between Internet Protocol end-points and a system which hosts at least two processes, each process of the system including a similar instruction set constituting a service application and each process having an IP address, wherein at least one process may adopt an active state where a plurality of connections are used for sending and receiving data while at least one other process may adopt a stand-by state where a plurality of connections are not used for sending and receiving data, the method including: replicating data from the at least one active process to the at least one stand-by process, the replicated data including status data of the connections of the active process, so that the stand-by process maintains its connections updated with said replicated data, and the replicated data further including status data of the instruction set constituting the service application in the at least one active process, so that the instruction set constituting the service application in the at least one stand-by process remains updated with said replicated data, and deactivating the IP address of the active process and activating the IP address of the stand-by process in case the active process becomes unavailable.

System Of Connecting Multiple Processors In Cascade

US Patent:
2002013, Sep 26, 2002
Filed:
Jan 25, 2001
Appl. No.:
09/772112
Inventors:
Isaac Wong - Fremont CA, US
International Classification:
G05B015/02
US Classification:
700/008000
Abstract:
A multiprocessor system uses a master processor coupled to a ROM device to transfer boot code to slave processors over a bus. The memory controllers in the slave processors are controlled to deny processor memory request until the boot code has been transferred to their RAM devices. The memory controllers map the transferred boot codes to a first address space in their RAM devices.

Automatic Configuration Of Delay Parameters For Memory Controllers Of Slave Processors

US Patent:
2002013, Sep 26, 2002
Filed:
Jan 25, 2001
Appl. No.:
09/772113
Inventors:
Isaac Wong - Fremont CA, US
International Classification:
G06F019/00
G01R027/28
G01R031/00
G01R031/14
US Classification:
702/119000
Abstract:
A method for automatically selecting delays for slave processors' memory controllers in a multiprocessor system is presented. A master processor coupled to the slave processors on a bootstrap bus commands the slave processors' memory controllers to select the delays. Various delay parameters are tested to select optimal delay parameter values.

Method And Apparatus For Forwarding Data Packets Addressed To A Cluster Servers

US Patent:
2005016, Jul 28, 2005
Filed:
Dec 24, 2003
Appl. No.:
10/746750
Inventors:
Isaac Wong - San Jose CA, US
International Classification:
G06F015/16
US Classification:
709201000, 709245000
Abstract:
Methods and apparatus are disclosed for forwarding a data packet addressed to a cluster of servers. According to one disclosed method, when a connection request is received from a client, a connection identifier is formed according to the connection request. The connection request is forwarded to a first-identified server in the cluster of servers. The connection identifier is associated with a responding server in the cluster of servers. Subsequent traffic received from the client associated with the connection identifier is forwarded to the responding server associated with the connection identifier.

Method And Apparatus For Providing Redundant Connection Services

US Patent:
2005028, Dec 22, 2005
Filed:
Jun 22, 2004
Appl. No.:
10/874665
Inventors:
Isaac Wong - San Jose CA, US
International Classification:
G06F015/173
G06F015/16
US Classification:
709224000, 709227000
Abstract:
A connection from a client to a primary server is monitored and state information pertaining to a protocol stack used in the primary server is conveyed to a standby server. When the primary server becomes unhealthy, a crossover message is sent by the standby server to a client according to the conveyed state information.

Automatic Configuration Of Delay Parameters In A Dynamic Memory Controller

US Patent:
6370067, Apr 9, 2002
Filed:
Jan 25, 2001
Appl. No.:
09/772111
Inventors:
Isaac H. Wong - Fremont CA
Keith V. Ngo - Gilroy CA
Jau-Wen Ren - Saratoga CA
Assignee:
Ishoni Networks, Inc. - Santa Clara CA
International Classification:
G11C 700
US Classification:
365194, 365233, 365201
Abstract:
A memory controller configured according to a delay pair for communicating with a memory device automatically selects optimal delay pairs by testing whether successful communication exists at various values for the delay pairs. The resulting set of delay pairs allowing successful communication are divided into a boundary set and non-boundary set. An optimal delay pair from the non-boundary set is chosen according to its relationship to delay pairs in the boundary set.

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