James E Bowles1004 Elder Cir, Austin, TX 78733

2006005, Mar 16, 2006

Apr 6, 2005

11/100299

Mark Bohm - Village of Bear Creek TX, US
Mark Fu - Newark CA, US
Henry Wurzburg - Austin TX, US
James Bowles - Austin TX, US
Robert Hollingsworth - Smithtown NY, US
Drew Dutton - Austin TX, US

H04L 12/50

370360000

In various embodiments, devices coupled to upstream ports may enumerate the USB switching hub according to the total number of downstream ports on the USB switching hub. In some embodiments, when a first upstream port is communicating with a first downstream port, status registers coupled to the second upstream port may indicate to the second upstream device that the first downstream port is disconnected. By enumerating the USB switching hub according to the total number of downstream ports, the upstream devices may not have to reenumerate the hub (and correspondingly each device coupled to the hub) each time a downstream device is switched. In some embodiments, an intelligent port routing switch may delay switching communications for the downstream port if there is an active transfer in progress between a related downstream port and an upstream port.

2006005, Mar 16, 2006

Sep 14, 2004

10/940406

Henry Wurzburg - Austin TX, US
James Bowles - Austin TX, US
Robert Hollingsworth - Smithtown NY, US
Mark Bohm - Village of Bear Creek TX, US
Drew Dutton - Austin TX, US

G06F 13/20

710313000

In various embodiments, a USB switching hub may switch between a first configuration and a second configuration to switch access between two or more upstream ports on the hub to at least a subset of downstream ports on the hub. In some embodiments, the hub may include a downstream routing controller to switch between the first configuration and the second configuration. In some embodiments, configurations (e.g., hardwired in the USB switching hub) may be switched as determined by logic on the USB switching hub.

2006022, Oct 12, 2006

Jun 14, 2006

11/424179

Mark Bohm - Village of Bear Creek TX, US
Mark Fu - Newark CA, US
Henry Wurzburg - Austin TX, US
James Bowles - Austin TX, US
Robert Hollingsworth - Smithtown NY, US
Drew Dutton - Austin TX, US
Akhlesh Nigam - Austin TX, US

H04L 12/28
H04L 12/56

370351000, 370401000

In various embodiments, devices coupled to upstream ports may enumerate the USB switching hub according to the total number of downstream ports on the USB switching hub. In some embodiments, when a first upstream port is communicating with a first downstream port, status registers coupled to the second upstream port may indicate to the second upstream device that the first downstream port is disconnected. By enumerating the USB switching hub according to the total number of downstream ports, the upstream devices may not have to re-enumerate the hub (and correspondingly each device coupled to the hub) each time a downstream device is switched. In some embodiments, an intelligent port routing switch may delay switching communications for the downstream port if there is an active transfer in progress between a related downstream port and an upstream port.

5740400, Apr 14, 1998

Jun 5, 1995

8/462985

James E. Bowles - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

G06F 1200

395471

A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, wherein the level 2 cache is connected to a main memory and wherein the level 1 cache is connected to a bus master. For each bus master, there is one level 1 cache assigned to it, and there is a shared level 2 cache that each of the level 1 caches are connected to. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.

5530597, Jun 25, 1996

Nov 30, 1994

8/346834

James E. Bowles - Austin TX
Mark Luedtke - Del Valle TX
Dale E. Gulick - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 946

395735

An apparatus for enabling an interrupt under certain hardware condition even though the interrupt has been masked by software, includes structure for indicating a software condition, structure for indicating a hardware condition, and structure, that is responsive to both aforementioned structures, for generating an interrupt in response to the assertion of an interrupt request signal.

5233613, Aug 3, 1993

Jun 26, 1991

7/725233

Bruce R. Allen - Buda TX
Arthur B. Oliver - Austin TX
Robert W. O'Dell - Austin TX
James E. Bowles - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1100

371 163

In a watchdog timer, the selected codes identifying the format of a watchdog timer algorithm, such as the intervals within which a watchdog timer status must be issued by the host processor, are supplied as hardwired preset codes in programmable fuse or read only memory cells that are adapted to be programmed, but are immune from ESD, power glitches and errant software. A programmable code indicating a programmable time interval is also stored in a register protected from errant software when the watchdog timer is enabled. A selector receives the preset code and the programmable code and selects an output code indicating the time interval within which the watchdog timer must be reset by a processor status signal. The selector can be programmed to select only the preset code by supplying a selector control signal through an element that is immune from electrostatic discharge, power glitches and errant software. Also, a code fixing the watchdog timer in an on state can be supplied with ESD-immune cells.

5408639, Apr 18, 1995

Jul 21, 1992

7/917489

Dale E. Gulick - Austin TX
James E. Bowles - Austin TX

Advanced Micro Devices - Austin TX

G06F 1300

395550

A processing system of the type having a processor which accesses external memory for data and/or instructions which includes an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of the processing system. The control system includes a selectably programmable clock for providing a clock signal of one of at least two speeds for determining the external memory access rate. The control system also includes enable duration control structure coupled to the selectably programmable clock. The enable duration control structure is arranged to enable the external memory for time durations during each memory access which are independent from the external memory access rate. Further, the enable duration control structure includes substructure for changing the duty cycle of external memory enable time duration control signals based upon the selected clock speed.

5796980, Aug 18, 1998

Feb 22, 1996

8/605741

James E. Bowles - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

G06F 1200

395471

A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, has a level 2 cache connected to a main memory and a level 1 cache connected to a bus master. Each bus master has one level 1 cache assigned to it. A shared level 2 cache is connected to each of the level 1 caches. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache, and whether that data has been modified. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access, and if the corresponding data has been modified. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.