James Wai Chow, 70438 21St St, San Francisco, CA 94121

6490005, Dec 3, 2002

Jun 30, 2000

09/607493

James Chow - Palo Alto CA
Kenny Wen - San Jose CA
Khin Lay - Santa Clara CA

STMicroelectronics, Inc. - Carrollton TX

H03M 112

348572, 348574

An analog-to-digital converter (ADC) ( ) for sampling high speed video signals includes Pre-amplifiers ( ) electrically coupled to Post-amplifiers ( ) that are electrically coupled to output latches ( and ). A sampling clock signal ( ) clocks the output latches ( and ) to sample an input analog electronic signal to provide a digital representation thereof. The ADC ( ) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers ( ) during a video signal horizontal blanking time period. The ADC ( ) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers ( ) increasing bit resolution. The ADC ( ) includes wired interconnect interpolation between the Pre-amplifiers ( ) and Post-amplifiers ( ) and between the Post-amplifiers ( ) and the output latches ( and ).

6836149, Dec 28, 2004

Apr 12, 2002

10/121625

James Chow - Palo Alto CA

STMicroelectronics, Inc. - Carrollton TX

H03K 190175

326 83, 326 37, 326 86, 326 90

An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources ( ) and a plurality of selectable current sources ( ), for selecting, in response to an input signal at the selection control input, at least one of an operating D. C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

6985016, Jan 10, 2006

Aug 18, 2004

10/921242

James Chow - Palo Alto CA, US
Kenny Wen - San Jose CA, US

STMicroelectronics, Inc. - Carrollton TX

H03L 7/06

327149, 327153, 327158, 327162

A closed loop delay line system () includes a phase lock loop that provides a phase lock output signal (). A delay line () includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input () adjusts the speed of the delay line (). A phase detector () compares phase between a first timing signal input () and the delay line output (). A bias adjust circuit () mixes the phase compare output signal () and the phase lock output signal () to provide a combination bias signal () to the delay line (). Additionally, the relative timing position of strobe outputs () from the delay line () can be individually adjusted.

6992508, Jan 31, 2006

Jun 25, 2004

10/877543

James Chow - Palo Alto CA, US

STMicroelectronics, Inc. - Carrollton TX

H03K 19/094

326 86, 326 82, 326 83, 326 90, 345204

An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources () and a plurality of selectable current sources (), for selecting, in response to an input signal at the selection control input, at least one of an operating D. C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

7373451, May 13, 2008

Dec 8, 2004

11/007911

Monica Sin-Ling Lam - Menlo Park CA, US
Constantine Paul Sapuntzakis - Mountain View CA, US
Ramesh U. V. Chandra - Palo Alto CA, US
Nickolai Borisovich Zeldovich - Stanford CA, US
Mendel Rosenblum - Stanford CA, US
James Eugene Chow - San Jose CA, US
David James Brumley - Pittsburgh PA, US

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

G06F 12/00

711 6, 709220

A cache-based system management architecture named “the Collective” automates system management and supports mobile computing. The Collective manages systems by manipulating virtual appliances, each encapsulating a system state. A virtual appliance (VA) may comprise a virtual network of VAs. Distributed repositories separately storing the VAs and user data. Publishers create and maintain VAs. A user plugs a bootable portable storage device implementing a VA transceiver (VAT) into a host computer. The VAT, comprising a Manager, a Cache Client, and a virtual machine monitor (VMM), authenticates the user, retrieves a copy of the latest version of a subscribed VA from the appropriate network repository, obtains user data, and automatically backs up the user data over the network in the background while running the subscribed VA. Multiple VAs can be run at the same time. With the novel caching protocol and cache charging process, the Collective performs well and has numerous advantages.

7890689, Feb 15, 2011

Mar 6, 2008

12/043672

Monica Sin-Ling Lam - Menlo Park CA, US
Constantine Paul Sapuntzakis - Mountain View CA, US
Ramesh U. V. Chandra - Belmont CA, US
Nickolai Borisovich Zeldovich - Redwood City CA, US
Mendel Rosenblum - Stanford CA, US
James Eugene Chow - San Mateo CA, US
David James Brumley - Pittsburgh CA, US

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

G06F 12/00

711 6, 711118, 718 1

Various approaches for virtual appliance management are described. In one approach a virtual appliance repository stores one or more virtual appliances and is coupled to the host computer via a network. A storage device stores a transceiver program capable when executed on said host computer of requesting and receiving the virtual appliances, and generating for each received virtual appliance a respective local copy on the host computer of each received virtual appliance. The local copy is private to the host computer. The transceiver program further binds the virtual appliances to the host computer and obtains user data relevant to the virtual appliances. The transceiver program runs each of the virtual appliances from the respective private local copies on the host computer.

8321842, Nov 27, 2012

Jun 27, 2008

12/163513

Min Xu - Palo Alto CA, US
Dmitry Grinberg - Mountain View CA, US
Vyacheslav Malyugin - Los Gatos CA, US
Petr Vandrovec - Mountain View CA, US
Ganesh Venkitachalam - Mountain View CA, US
Boris Weissman - Mountain View CA, US
Andrew Biggadike - Palo Alto CA, US
James Chow - San Jose CA, US

VMware, Inc. - Palo Alto CA

G06F 9/44
G06F 9/455

717127, 717124, 718 1

Replay-time-only functionalities in a computer program are executed only during replay in a virtual machine and are skipped outside of replay. If a replay-time-only functionality is detected during the replay of a program execution in a virtual machine, the replay may be paused and the virtual machine state may be saved. The replay-time-only core functionality is executed. When this execution is complete, a prior state of the virtual machine may be restored and the replay may be resumed.

2002018, Dec 5, 2002

May 29, 2001

09/867793

James Chow - Palo Alto CA, US
Kenny Wen - San Jose CA, US

H04L001/22
G11B005/00
G06K005/04
G11B020/20

714/700000

A closed loop delay line system () includes a phase lock loop that provides a phase lock output signal (). A delay line () includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input () adjusts the speed of the delay line (). A phase detector () compares phase between a first timing signal input () and the delay line output (). A bias adjust circuit () mixes the phase compare output signal () and the phase lock output signal () to provide a combination bias signal () to the delay line (). Additionally, the relative timing position of strobe outputs () from the delay line () can be individually adjusted.