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James C Fye, 635901 Bloomfield Rd, Scottsdale, AZ 85254

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5901 Bloomfield Rd, Scottsdale, AZ 85254    480-5961472   

Phoenix, AZ   

Fort Gratiot, MI   

Glen Burnie, MD   

Maricopa, AZ   

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James C Fye

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Company: United states marine corps Position: Engineer

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Degree: High school graduate or higher

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James Fye Photo 26

Engineer

Industry:
Military
Work:
United States Marine Corps
Engineer

Publications & IP owners

Us Patents

Architecture For Multi-Channel Video Processing

US Patent:
2005009, May 5, 2005
Filed:
Oct 30, 2003
Appl. No.:
10/699311
Inventors:
James Fye - Scottsdale AZ, US
International Classification:
H04N007/173
H04N007/16
US Classification:
725118000, 725100000, 725131000, 725139000, 725151000
Abstract:
One embodiment includes an apparatus for display of video data from a designated number of an N number of video channels. The apparatus comprises an N number of video decoders to receive the video data from the N number of video channels. A designated number of the N number of video decoders to decode the video data from the designated number of the N number of video channels. The apparatus also comprises a P number of video processing pipelines coupled to the N number of video decoders through a switch network. The switch network configured to connect any of the outputs from the N number of video decoders to any of the inputs into the P number of video processing pipelines.

Shared-Resource Time Partitioning In A Multi-Core System

US Patent:
2009021, Aug 27, 2009
Filed:
Feb 21, 2008
Appl. No.:
12/035062
Inventors:
Larry J. Miller - Black Canyon City AZ, US
James C. Fye - Scottsdale AZ, US
Assignee:
HONEYWELL INTERNATIONAL INC. - Morristown NJ
International Classification:
G06F 9/46
US Classification:
718104
Abstract:
An improvement to computing systems is introduced that allows a hardware controller to be configured to time partition a shared system resource among multiple processing elements, according to one embodiment. For example, a memory controller may partition shared memory and may include processor-accessible registers for configuring and storing a rate of resource budget replenishment (e.g. size of a repeating arbitration window), a time budget allocated among each entity that shares the resource, and a selection of a hard or soft partitioning policy (i.e. whether to utilize slack bandwidth). An additional feature that may be incorporated in a main-memory-access time-partitioning application is an accounting policy to ensure that cache write-backs prompted by snoop transactions are charged to the data requester rather than to the responder. Additionally, an arbiter may prioritize requests from particular requesting entities.

Single Bus Architecture Supporting Subsystems Of Various Criticality Levels

US Patent:
5841969, Nov 24, 1998
Filed:
Aug 13, 1996
Appl. No.:
8/696419
Inventors:
James C. Fye - Scottsdale AZ
Assignee:
Honeywell Inc.
International Classification:
G06F 1114
US Classification:
39518509
Abstract:
Communications systems architecture using a single shared resource bus to interconnect a plurality of subsystems each handling information having a first predetermined importance level and an error detect wrapper for encoding information to and from each such subsystem to detect errors in transmission along the shared resource bus. A heartbeat monitor is also provided for use in those subsystems handling information having a second predetermined level of importance to disable the subsystem if an error occurs within the subsystem.

Method And Apparatus For Robust Data Broadcast On A Peripheral Component Interconnect Bus

US Patent:
5983024, Nov 9, 1999
Filed:
Nov 26, 1997
Appl. No.:
8/978777
Inventors:
James Calvin Fye - Scottsdale AZ
Assignee:
Honeywell, Inc. - Minneapolis MN
International Classification:
G06F 1300
US Classification:
395856
Abstract:
A method of robust data broadcasting on a peripheral component interconnect(PCI) bus sets intended target agents to snoop the broadcast transaction in which the master agent also responds as the target agent.

Methods Of Vestibulo-Ocular Reflex Correction In Display Systems

US Patent:
2017012, May 4, 2017
Filed:
Oct 28, 2015
Appl. No.:
14/925012
Inventors:
- Morris Plains NJ, US
Ken Leiphon - Phoenix AZ, US
James C. Fye - Scottsdale AZ, US
Jerry Ball - Peoria AZ, US
William Ray Hancock - Phoenix AZ, US
Assignee:
HONEYWELL INTERNATIONAL INC. - Morris Plains NJ
International Classification:
G02B 27/01
G06F 3/01
G06F 3/038
B64D 43/00
Abstract:
A method for displaying images on a head-mounted display (HMD) device that compensates for a user's vestibulo-ocular reflex (VOR) response. The displayed HMD image is compensated for predicted eye position such that the displayed image stays centered on the fovea of the eye, during transient eye movement caused by head motion, resulting in better display readability, discernment and cognitive processing.

Low Latency Augmented Reality Display

US Patent:
2016011, Apr 21, 2016
Filed:
Oct 21, 2014
Appl. No.:
14/519457
Inventors:
- Morristown NJ, US
James C. Fye - Scottsdale AZ, US
Ken Leiphon - Phoenix AZ, US
Assignee:
HONEYWELL INTERNATIONAL INC. - Morristown NJ
International Classification:
G06T 19/00
G06T 3/40
G06T 1/60
G06T 19/20
Abstract:
An augmented reality system is provided and a method for controlling an augmented reality system are provided. The augmented reality system, for example, may include, but is not limited to a display, a memory, and at least one processor communicatively coupled to the display and memory, the at least one processor configured to generate image data having a first resolution at a first rate, store the generated image data in the memory, and transfer a portion of the generated image data having a second resolution to the display from the memory at a second rate, wherein the second rate is faster than the first rate and the second resolution is smaller than the first resolution. This dual rate system then enables a head-tracked augmented reality system to be updated at the high rate, reducing latency based artifacts.

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