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John M Kaczmarczyk, 621005 Southern Pines Dr, Endicott, NY 13760

John Kaczmarczyk Phones & Addresses

1005 Southern Pines Dr, Endicott, NY 13760    607-7485454   

908 Sarah Ln, Endicott, NY 13760    607-7485454   

Endwell, NY   

1504 Cherry Hill Dr, Poughkeepsie, NY 12603   

Binghamton, NY   

Washington, DC   

Mahanoy City, PA   

1005 Southern Pines Dr, Endicott, NY 13760    607-5428888   

Work

Company: Affairs unlimited catering May 1988 Position: Entrepreneur / owner / executive chef

Education

School / High School: Culinary Institute of America- Hyde Park, NY 1984 Specialities: Culinary Arts

Skills

17 year member Weston Volunteer Fire Department MRT certified

Emails

Mentions for John M Kaczmarczyk

John Kaczmarczyk resumes & CV records

Resumes

John Kaczmarczyk Photo 27

Senior Engineering Manager

Location:
Ithaca, NY
Industry:
Semiconductors
Work:
IBM
Senior Engineering Manager
Education:
Drexel University 1979 - 1984
Skills:
Management, Unix, Program Management, Asic, Semiconductors, Perl, Embedded Systems, Soc, Debugging, Software Development, Project Management, Integration, Linux, Cross Functional Team Leadership, C
John Kaczmarczyk Photo 28

John A Kaczmarczyk

Work:
Geraldine 1977 - 1998
President
John Kaczmarczyk Photo 29

John Kaczmarczyk

John Kaczmarczyk Photo 30

John Kaczmarczyk - Wilton, CT

Work:
Affairs Unlimited Catering May 1988 to 2000
Entrepreneur / Owner / Executive Chef
Education:
Culinary Institute of America - Hyde Park, NY 1984 to 1986
Culinary Arts
Florida International University - Miami, FL 1978 to 1982
B.S. in Hospitality Management
Skills:
17 year member Weston Volunteer Fire Department MRT certified

Publications & IP owners

Us Patents

Efficient, Flexible Motion Estimation Architecture For Real Time Mpeg2 Compliant Encoding

US Patent:
6549575, Apr 15, 2003
Filed:
Nov 7, 1996
Appl. No.:
08/745584
Inventors:
Adrian Stephen Butter - Binghamton NY
John Mark Kaczmarczyk - Endicott NY
Agnes Yee Ngai - Endwell NY
Edward Francis Westermann - Endicott NY
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation. - Armonk NY
International Classification:
H04N 732
US Classification:
37524016
Abstract:
Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

On-Chip Dynamic Buffer Level Indicators For Digital Video Encoder

US Patent:
6961378, Nov 1, 2005
Filed:
Nov 5, 1998
Appl. No.:
09/186584
Inventors:
James D. Greenfield - Binghamton NY, US
John M. Kaczmarczyk - Endicott NY, US
Agnes Y. Ngai - Endwell NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04N007/32
US Classification:
37524016
Abstract:
Method and encoder for encoding a digital video image stream. The encoding includes spatial compression of still images in the video stream and temporal compression between the still images. The spatial compression is carried out by converting a time domain image of a macroblock to a frequency domain image of the macroblock, taking the discrete cosine transform of the frequency domain image, transforming the discrete cosine transformed macroblock image by a quantization factor, and run length encoding the quantized discrete cosine transformed macroblock image. The temporal compression is carried out by reconstructing the run length encoded, quantized, discrete cosine transformed image of the macroblock, searching for a best match macroblock, and constructing a motion vector between them. This forms a bitstream of run length encoded, quantized, discrete cosine transform macroblocks and of motion vectors. This bitstream is passed to and through an external buffer to a transmission medium.

Dynamically Switching Quant Matrix Tables Within An Mpeg-2 Encoder

US Patent:
6999511, Feb 14, 2006
Filed:
Feb 23, 1999
Appl. No.:
09/255892
Inventors:
Charles Edward Boice - Endicott NY, US
James David Greenfield - Binghamton NY, US
John Mark Kaczmarczyk - Endicott NY, US
Agnes Yee Ngai - Endwell NY, US
Stephen Philip Pokrinchak - Owego NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04B 1/66
US Classification:
375240, 37524005, 37524007, 37524004, 37524006, 37524003, 382251, 382235
Abstract:
A digital video encoder is presented adapted for dynamically switching between sets of quantizer matrix tables without pausing encoding of a stream of video data. Two or more sets of quantizer matrix tables are held at the encoder's quantization unit and compressed store interface for dynamically switching between sets of quant matrix tables at a picture boundary of the sequence of video data, i. e. , without stopping encoding of the sequence of video data. Further, while one set of matrix tables is being employed to quantize the stream of video data, the encoder can be updating or modifying another set of quantization matrix tables, again without stopping encoding of the sequence of video data.

Method To Compensate For A Fade In A Digital Video Input Sequence

US Patent:
6040875, Mar 21, 2000
Filed:
Mar 23, 1998
Appl. No.:
9/046290
Inventors:
Charles E. Boice - Endicott NY
John M. Kaczmarczyk - Endicott NY
Agnes Y. Ngai - Endwell NY
Michael P. Vachon - Johnson City NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04N 974
H04N 712
H04N 514
US Classification:
348595
Abstract:
A method to compensate for a fade in a digital video input sequence is provided where the video input sequence is to be compressed according to the MPEG-2 video compression standard. The method comprises a first step of dividing each frame of a current frame into two fields. In a second step, each field of the current frame is divided into at least one field band. In a third step, the luminance and chrominance pixel values are individually summed for the pixels in each field of the current frame. In a fourth step, the luminance pixel values are summed for the pixels in each field band of the current frame. In a fifth step, each respective field band sum and field sum of the current frame is compared with that of the previous frame in the video input sequence. In a sixth step, detection of whether or not a fade has occurred is provided, based upon the comparison in the fifth step. In a seventh step, the encoding algorithm is adjusted if a fade has occurred.

Circuit And Method For Differentiating Multiple Modules

US Patent:
6127851, Oct 3, 2000
Filed:
Jan 26, 1999
Appl. No.:
9/238090
Inventors:
Charles Edward Boice - Endicott NY
John Mark Kaczmarczyk - Endicott NY
Michael Patrick Vachon - Johnson City NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2500
US Classification:
326101
Abstract:
More than 2 power N external conditions are determined by a circuit package. Connections are made from N inputs to either a first or second contact at either a first or second logic state respectively or to digital outputs. The outputs may be sequentially placed at either the first or second logic state. By recording an indication signal from the inputs an electronic circuit is adapted to determine more than 2 power N conditions.

Scalable Mpeg2 Compliant Video Encoder

US Patent:
5768537, Jun 16, 1998
Filed:
Feb 22, 1996
Appl. No.:
8/605559
Inventors:
Adrian Stephen Butter - Binghamton NY
John Mark Kaczmarczyk - Endicott NY
Agnes Yee Ngai - Endwell NY
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04N 730
H04N 732
H04N 750
US Classification:
39520077
Abstract:
A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

Apparatus And Method For Power Reduction Control In A Video Encoder Device

US Patent:
6301671, Oct 9, 2001
Filed:
Mar 23, 1998
Appl. No.:
9/046287
Inventors:
Charles Edward Boice - Endicott NY
John Mark Kaczmarczyk - Endicott NY
John Ashley Murdock - Apalachin NY
Michael Patrick Vachon - Johnson City NY
Robert Leslie Woodard - Newark Valley NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 132
US Classification:
713322
Abstract:
System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

Adaptive Real-Time Encoding Of Video Sequence Employing Image Statistics

US Patent:
6040861, Mar 21, 2000
Filed:
Oct 10, 1997
Appl. No.:
8/948442
Inventors:
Lilla Boroczky - Endicott NY
Charlene Ann Gebler - Vestal NY
John M. Kaczmarczyk - Endicott NY
Edward F. Westermann - Endicott NY
Robert L. Woodard - Newark Valley NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04N 718
US Classification:
348409
Abstract:
Method, system and computer program product are provided for adaptively encoding in hardware, software or a combination thereof a sequence of video frames in real-time. A first encoding subsystem is employed to analyze the sequence of video frames to derive information on at least one characteristic thereof, such as motion statistics, non-motion statistics, scene change statistics, or scene fade statistics. The gathered information may comprise either an intraframe characteristic or an interframe characteristic. A second encoding subsystem, coupled to the first encoding subsystem, encodes the sequence of video frames employing at least one controllable parameter. The second encoding subsystem dynamically adapts intraframe or interframe encoding of the sequence of video frames by adjusting the at least one controllable parameter used in the encoding process in response to the derived information from the first encoding subsystem.

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