James Shingle Koford, 862018 Woodbridge Ln, Lincoln, CA 95648

6407434, Jun 18, 2002

Aug 21, 1995

08/517142

Michael D. Rostoker - Boulder Creek CA
James S. Koford - Mountain View CA
Ranko Scepanovic - San Jose CA
Edwin R. Jones - Sunnyvale CA
Ashok K. Kapoor - Palo Alto CA
Valeriy B. Kudryavtsev - Moscow, RU
Alexander E. Andreev - Moskovskata Oblast, RU
Stanislav V. Aleshin - Moscow, RU
Alexander S. Podkolzin - Moscow, RU

LSI Logic Corporation - Milpitas CA

H01L 2144

257401, 257207, 257211, 257758, 257776, 438180

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60Â. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed.

6493658, Dec 10, 2002

Apr 19, 1994

08/229616

James S. Koford - San Jose CA
Michael D. Rostoker - Boulder Creek CA
Edwin R. Jones - Sunnyvale CA
Douglas B. Boyle - Palo Alto CA
Ranko Scepanovic - Cupertino CA

LSI Logic Corporation - Milpitas CA

G06F 1750

703 1, 716 9, 716 10

A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.

6557145, Apr 29, 2003

Mar 6, 2001

09/801010

Douglas B. Boyle - Palo Alto CA
James S. Koford - San Jose CA

Monterey Design Systems, Inc. - Sunnyvale CA

G06F 1750

716 2, 716 7, 716 8

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

6999910, Feb 14, 2006

Nov 20, 2001

10/015194

James S. Koford - San Jose CA, US
Christopher L. Hamlin - Los Gatos CA, US

LSI Logic Corporation - Milpitas CA

G06G 7/48

703 13, 703 14, 716 10

The present invention is directed to a comprehensive design flow system. A system and method are provided that provide a comprehensive system to introduce a metamethodology that integrates EDA design tools into a manageable and predictable design flow. A method of designing an integrated circuit may include accessing a design utility operating on an information handling system, displaying a dynamic template on a display device of an information handling system, wherein the dynamic template implements at least two symbols displayable on a display device, in which the at least two symbols each correspond to a respective EDA tool, and arranging the at least two symbols displayed on the display device. The at least two symbols are arranged to indicate an interrelationship of the EDA tools in a design process of an integrated circuit.

7076746, Jul 11, 2006

Jan 29, 2004

10/768558

Christopher L. Hamlin - Los Gatos CA, US
James S. Koford - San Jose CA, US

LSI Logic Corporation - Milpitas CA

G06F 17/50

716 3

The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process.

2004002, Feb 5, 2004

Jul 31, 2002

10/210188

James Koford - Mountain View CA, US
Christopher Hamlin - Los Gatos CA, US
Michael Eneboe - San Jose CA, US

G06F017/50

716/012000

A method for designing an integrated circuit includes selecting representations of integrated circuit components from a plurality of integrated circuit component representations, the representations suitable for being displayed on a display device. Connections are indicated between at least a portion of the selected representations of the integrated circuit components. An integrated circuit description is provided including the selected representations and the indicated connections between the representations, wherein the integrated circuit description includes data obtained from a database having characteristic data corresponding to the plurality of representations.

2005003, Feb 10, 2005

Jan 29, 2004

10/768588

Christopher Hamlin - Los Gatos CA, US
James Koford - San Jose CA, US
Douglas Boyle - Palo Alto CA, US

G06F017/50
G06F009/45

716003000, 716004000, 716006000

The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, availability of required features of a design in a target foundry process may be checked. The target foundry process must provide all the features that are used in the design. The design may include base wafer layers and metal stack layers. Then, a base wafer/metal stack interface layer for the design may be selected. Next, compatible blocks between different base wafer processes may be created. Then, a physical design library for the design may be created. Next, a logic design and timing library for the design may be created. This way, the design may be mapped to different foundry processes.

5631581, May 20, 1997

Dec 6, 1995

8/567952

Michael D. Rostoker - Boulder Creek CA
James S. Koford - Mountain View CA
Ranko Scepanovic - San Jose CA
Edwin R. Jones - Sunnyvale CA
Ashok K. Kapoor - Palo Alto CA
Valeriy B. Kudryavtsev - Moscow, RU
Alexander E. Andreev - Moskovskata Oblast, RU
Stanislav V. Aleshin - Moscow, RU
Alexander S. Podkolzin - Moscow, RU

LSI Logic Corporation - Milpitas CA

H03K 17093

326101

A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery. First and second terminals are formed in the active area adjacent to two vertices of the triangle respectively, and first to third gates are formed between the first and second terminals. The gates have contacts formed outside the active area adjacent to a side of the triangle between the two vertices. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor are selected for each device to provide a desired AND, NAND, OR or NOR function. A third terminal can be formed between two of the gates and used as an output terminal to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.