James P Laudon, 60Boulder, CO

7281096, Oct 9, 2007

Feb 9, 2005

11/054850

Ramaswamy Sivaramakrishnan - San Jose CA, US
Sunil Vemula - Sunnyvale CA, US
Sanjay Patel - Fremont CA, US
James P. Laudon - Madison WI, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 13/14

711152, 711200

A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

7454631, Nov 18, 2008

Mar 11, 2005

11/078570

James P. Laudon - Madison WI, US
Curtis R. McAllister - Los Altos CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 1/00
G06F 1/26
G06F 9/46

713300, 713320, 718100, 718102

A system is provided for detecting when a temperature of a multiprocessor chip approaches an established threshold temperature indicating an imminent overheat condition. When the threshold temperature is reached, a number of active threads are idled in order to remove their contribution from the overall power consumption of the multiprocessor chip. Idling of the threads serves to prevent the multiprocessor chip from reaching the overheat condition. Once the temperature of the multiprocessor chip drops to an acceptable level, execution of the previously idled threads is resumed. Detection of the imminent overheat condition and corresponding idling of the threads to avoid reaching the overheat condition is conducted by hardware to ensure timely reduction of the multiprocessor chip temperature.

7574566, Aug 11, 2009

Sep 21, 2006

11/524837

James P. Laudon - Madison WI, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 13/00
G06F 13/28

711141

Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence information to the processor thread of the processing unit. After receiving the trap signal and the coherence information, the processor thread may perform a cache coherence operation for the memory request using at least the received coherence information. The processing unit may include a plurality of processor threads and a load balancer. The load balancer may receive coherence requests from one or more remote processing units and distribute the received coherence requests across the plurality of processor threads. The load balance may preferentially distribute the received coherence requests across the plurality of processor threads based on the operation state of the processor threads.

8195903, Jun 5, 2012

Jun 29, 2006

11/477733

James P. Laudon - Madison WI, US

Oracle America, Inc. - Redwood City CA

G06F 12/14

711163, 711167, 711E12091

A memory controller including a control unit for limiting the number of memory requests that are executed within a predetermined time period to regulate power consumption. The control unit may determine a memory request limit indicating the maximum number of memory requests that are allowed to be executed during the predetermined time period based on at least a carry-over limit and a new request limit. The carry-over limit may indicate the maximum number of carry-over memory requests that are allowed during the predetermined time period. The new request limit may indicate the maximum number of new memory requests that are allowed during the predetermined time period. The control unit may further control the number of memory requests that are executed in each of a sequence of predetermined time periods.

2006013, Jun 22, 2006

Mar 30, 2005

11/095840

James Laudon - Madison WI, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 9/46

718100000

A multi-thread processor including a processing core. The processing core including multiple threads and a scheduler. The scheduler includes a thread state register. The thread state register being capable of storing a selective wait state for a selected one of the threads. A method of scheduling threads in a multi-thread processor is also disclosed.

2008001, Jan 17, 2008

Jul 12, 2006

11/484970

James P. Laudon - Madison WI, US
Adam R. Talcott - Los Altos CA, US
Sanjay Patel - Fremont CA, US
Thirumalai S. Suresh - Santa Clara CA, US

G06F 9/30

712217

In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management unit is configured to operate the plurality of storage locations as a plurality of windows, wherein register addresses encoded into the instructions identify storage locations among a subset of the plurality of storage locations that are within a current window. Additionally, the window management unit is configured to allocate a second window in response to a predetermined event. One of the current window and the second window serves as a checkpoint of register state, and the other one of the current window and the second window is updated in response to instructions processed subsequent to the checkpoint. The checkpoint may be restored if the speculative execution results are discarded.

5727150, Mar 10, 1998

Dec 17, 1996

8/766363

James P. Laudon - Menlo Park CA
Daniel E. Lenoski - San Jose CA

Silicon Graphics, Inc. - Mountain View CA

G06F 1300

39520008

A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is incremented, and then the second count is subtracted from the incremented first count to obtain a difference between the second count and the incremented first count. A comparator determines whether the difference is greater than a migration threshold value. If the difference is greater than the migration threshold value, then a migration interrupt is issued.

5680576, Oct 21, 1997

May 5, 1995

8/435460

James P. Laudon - Menlo Park CA

Silicon Graphics, Inc. - Mountain View CA

G06F 1208

395472

A multiprocessor system having a plurality of requestors, a memory and memory directory controller employing directory-based coherence. The system implements a method to detect dropping of clean-exclusive data. Only one intervention message is permitted to target an exclusive object held by a first requestor, wherein the intervention message is caused by a second requestor. The system detects whether the first requestor has an outstanding writeback for the object targeted by the intervention message, as well as whether the first requestor has a clean-exclusive, dirty-exclusive or invalid copy of the object targeted by the intervention message. A clean-exclusive copy of the object has been dropped when no outstanding writeback is detected and the first requestor has the object in the invalid state.