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James F Montanaro, 6919 Surfside Ave, Winthrop Hlds, MA 02152

James Montanaro Phones & Addresses

19 Surfside Ave, Winthrop, MA 02152   

Liverpool, NY   

65 Father Carney Dr, Milton, MA 02186   

Steubenville, OH   

Baldwinsville, NY   

Syracuse, NY   

Asbury, NJ   

Stafford, VA   

Boston, MA   

8203 Penelope Ln, Liverpool, NY 13090    315-6527868   

Mentions for James F Montanaro

James Montanaro resumes & CV records

Resumes

James Montanaro Photo 13

Manager Operational Excellence/Environment, Health & Safety

Location:
Rgion de Boston
Industry:
quipements mdicaux
James Montanaro Photo 14

James Montanaro

James Montanaro Photo 15

James Montanaro

Location:
Rgion de Austin, Texas
Industry:
Matriel informatique
James Montanaro Photo 16

Senior Research Engineer At Mantech

Location:
Rgion de Washington D.C. Metro
Industry:
Technologies et services de l'information
James Montanaro Photo 17

Independent Photography Professional

Location:
Rgion de Syracuse, New York
Industry:
Photographie
James Montanaro Photo 18

Owner At Montanaro's Golf Fix

Location:
Rgion de New York City
Industry:
Divertissements
James Montanaro Photo 19

James Montanaro

Publications & IP owners

Us Patents

Push-Pull Cascode Logic

US Patent:
5023480, Jun 11, 1991
Filed:
Jan 4, 1990
Appl. No.:
7/460818
Inventors:
Bruce A. Gieseke - Natick MA
Robert A. Conrad - Millbury MA
James J. Montanaro - Princeton MA
Daniel W. Dobberpuhl - Shrewsbury MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H03K 5153
H03F 345
US Classification:
307448
Abstract:
A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float. The channel types of the transistors may be reversed in another embodiment; the pull-down transistors of the differential amplifier may be N-channel and the logic and latching transistors P-channel.

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