James J Quinlivan, 66Melbourne, FL

6670263, Dec 30, 2003

Mar 10, 2001

09/802702

Arne W. Ballantine - Round Lake NY
Kevin K. Chan - Staten Island NY
Jeffrey D. Gilbert - Burlington VT
Kevin M. Houlihan - Boston MA
Glen L. Miles - Essex Junction VT
James J. Quinlivan - Essex Junction VT
Samuel C. Ramac - Poughkeepsie NY
Michael B. Rice - Colchester VT
Beth A. Ward - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 213205

438592, 438585, 438199, 438287, 438655

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

6706644, Mar 16, 2004

Jul 26, 2002

10/206427

Jay S. Burnham - East Fairfield VT
James S. Nakos - Essex Junction VT
James J. Quinlivan - Essex Junction VT
Steven M. Shank - Jericho VT
Deborah A. Tucker - Westford VT
Beth A. Ward - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 2131

438775, 782759, 782778

Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

6893948, May 17, 2005

Jul 11, 2003

10/616962

Arne W. Ballantine - Round Lake NY, US
Kevin K. Chan - Staten Island NY, US
Jeffrey D. Gilbert - Burlington VT, US
Kevin M. Houlihan - Boston MA, US
Glen L. Miles - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US
Samuel C. Ramac - Essex Junction VT, US
Michael B. Rice - Colchester VT, US
Beth A. Ward - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L021/20
H01L021/3205
H01L021/4763

438585, 438592, 438488

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

6893979, May 17, 2005

Mar 15, 2001

09/809663

Mukesh V. Khare - White Plains NY, US
Christopher P. D'Emic - Ossining NY, US
Thomas T. Hwang - Wappingers Falls NY, US
Paul C. Jamison - Hopewell Junction NY, US
James J. Quinlivan - Essex Junction VT, US
Beth A. Ward - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L021/31
H01L021/469

438769, 438775, 438786

A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

6909157, Jun 21, 2005

Sep 2, 2003

10/652307

Jay S. Burnham - East Fairfield VT, US
James S. Nakos - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US
Steven M. Shank - Jericho VT, US
Deborah A. Tucker - Westford VT, US
Beth A. Ward - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L029/76

257411, 257655

Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

6967167, Nov 22, 2005

Sep 30, 2003

10/605435

Peter J. Geiss - Underhill VT, US
Alvin J. Joseph - Williston VT, US
Xuefeng Liu - South Burlington VT, US
James S. Nakos - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L021/302

438704, 438706, 438715, 438723, 438743, 438744

A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i. e. , oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

7109559, Sep 19, 2006

Nov 5, 2004

10/982999

Mukesh V. Khare - White Plains NY, US
Christopher P. D'Emic - Ossining NY, US
Thomas T. Hwang - Wappingers Falls NY, US
Paul C. Jamison - Hopewell Junction NY, US
James J. Quinlivan - Essex Junction VT, US
Beth A. Ward - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 29/76
H01L 29/94

257411, 257649

A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

7138691, Nov 21, 2006

Jan 22, 2004

10/707897

Jay S. Burnham - Fletcher VT, US
John J. Ellis-Monaghan - Grand Isle VT, US
James S. Nakos - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 29/76

257410, 257369

A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.