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Julie D Walker, 5717455 W Rice Ave, Post Falls, ID 83854

Julie Walker Phones & Addresses

17455 W Rice Ave, Post Falls, ID 83854   

Hauser, ID   

Coeur d Alene, ID   

Kent, WA   

Hayden, ID   

Vancouver, WA   

Work

Company: Owen coning finished basement Address: 1301 A St Ste 600, Tacoma, WA 98402 Phones: 253-3837106 Position: Vice president Industries: Miscellaneous Food Stores

Languages

English

Mentions for Julie D Walker

Career records & work history

Medicine Doctors

Julie Walker Photo 1

Julie D Walker, Coeur D Alene ID - LCPC

Specialties:
Counseling
Address:
1090 W Park Pl, Coeur D Alene, ID 83814
208-2920303 (Phone)
Languages:
English

Publications & IP owners

Us Patents

Reduced Uncorrectable Memory Errors

US Patent:
2019037, Dec 5, 2019
Filed:
Jun 18, 2019
Appl. No.:
16/444480
Inventors:
- Santa Clara CA, US
Prashant S. DAMLE - Portland OR, US
Rajesh SUNDARAM - Folsom CA, US
Shekoufeh QAWAMI - El Dorado Hills CA, US
Julie M. WALKER - El Dorado Hills CA, US
Doyle RIVERS - El Dorado Hills CA, US
International Classification:
G06F 11/10
H03M 13/05
H03M 13/27
H03M 13/00
G06F 3/06
Abstract:
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Reduced Uncorrectable Memory Errors

US Patent:
2018025, Sep 6, 2018
Filed:
Mar 1, 2018
Appl. No.:
15/909929
Inventors:
- Santa Clara CA, US
Prashant S. DAMLE - Portland OR, US
Rajesh SUNDARAM - Folsom CA, US
Shekoufeh QAWAMI - El Dorado Hills CA, US
Julie M. WALKER - El Dorado Hills CA, US
Doyle RIVERS - El Dorado Hills CA, US
International Classification:
G06F 11/10
H03M 13/00
H03M 13/27
H03M 13/05
G06F 3/06
H03M 13/15
H03M 13/19
Abstract:
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

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