James Toner Sundby, 682970 Compton Pl, Tracy, CA 95377
James Sundby Phones & Addresses
2970 Compton Pl, Tracy, CA 95377 209-8354577
320 Gonzalez St, Tracy, CA 95376 209-8327486
San Jose, CA
Gardena, CA
Defense Dist Region, CA
San Joaquin, CA
2970 Compton Pl, Tracy, CA 95377
Work
Position:
Professional/Technical
Education
Degree:
High school graduate or higher
Mentions for James Toner Sundby
Publications & IP owners
Us Patents
Means To Detect A Missing Pulse And Reduce The Associated Pll Phase Bump
US Patent:
7646224, Jan 12, 2010
Filed:
May 4, 2007
Appl. No.:
11/744386
Inventors:
James Toner Sundby - Tracy CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7/06
US Classification:
327156, 327 18, 327147, 375373
Abstract:
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.
Means To Reduce The Pll Phase Bump Caused By A Missing Clock Pulse
US Patent:
7816958, Oct 19, 2010
Filed:
May 4, 2007
Appl. No.:
11/744420
Inventors:
James Toner Sundby - Tracy CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7/06
US Classification:
327156, 327147, 327157, 327158, 327161
Abstract:
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.
Means To Control Pll Phase Slew Rate
US Patent:
2008021, Sep 11, 2008
Filed:
Mar 5, 2007
Appl. No.:
11/681886
Inventors:
James Toner Sundby - Tracy CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7/00
US Classification:
331 17
Abstract:
A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin.
Means To Control Pll Phase Slew Rate
US Patent:
2008021, Sep 11, 2008
Filed:
Aug 2, 2007
Appl. No.:
11/833158
Inventors:
James Toner Sundby - Tracy CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7/06
US Classification:
331 17
Abstract:
A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin.
Means To Detect A Missing Pulse And Reduce The Associated Pll Phase Bump
US Patent:
2010015, Jun 24, 2010
Filed:
Nov 24, 2009
Appl. No.:
12/625406
Inventors:
James Toner Sundby - Tracy CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7/06
US Classification:
327156
Abstract:
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.
Rail-To-Rail Opamp With Large Sourcing Current And Small Quiescent Current
US Patent:
5315264, May 24, 1994
Filed:
May 10, 1993
Appl. No.:
8/060148
Inventors:
James T. Sundby - Tracy CA
Alexei N. Shkidt - Newark CA
Alexei N. Shkidt - Newark CA
Assignee:
Exar Corporation - San Jose CA
International Classification:
H03F 345
US Classification:
330253
Abstract:
A rail-to-rail CMOS operational amplifier with a large source current and small quiescent current. The CMOS opamp includes a folded cascode input structure, a negative slew detector and an output stage that acts as a push-pull output stage during slewing and a Class A output stage during small signal operation. The opamp can drive large capacitive loads (in excess of 0. 5. mu. F), with the load capacitor providing for the opamp frequency compensation.
Accurate Low Voltage Detect Circuit
US Patent:
5440254, Aug 8, 1995
Filed:
Oct 20, 1992
Appl. No.:
7/963867
Inventors:
James T. Sundby - Tracy CA
Assignee:
Exar Corporation - San Jose CA
International Classification:
H03K 5153
US Classification:
327 79
Abstract:
An accurate and stable low voltage detect circuit that provides a low voltage detect signal with minimal variation over process and temperature without trimming requirements. The power supply voltage is divided by a resistor voltage divider and compared to the output voltage of a bandgap reference circuit at the inputs of a comparator. The output of the comparator indicates power-on when the voltage divided power supply raises above the bandgap reference voltage. The low voltage detect circuit of the present invention will generate a correct low voltage detect signal even at power supply voltages too low for much of the rest of the circuit to operate properly. At low enough Vcc voltages, a transistor switch disconnects the resistor voltage divider from Vcc, causing all voltages taps off of the resistor voltage divider to drop to ground. Additionally, especially designed bandgap reference and comparator circuits ensure proper operation of the low voltage detect circuit at low power supply voltages.
Cmos Opamp With Large Sinking And Sourcing Currents And High Slew Rate
US Patent:
5325069, Jun 28, 1994
Filed:
Dec 29, 1992
Appl. No.:
7/998153
Inventors:
James T. Sundby - Tracy CA
Assignee:
Exar Corporation - San Jose CA
International Classification:
H03F 345
US Classification:
330253
Abstract:
A CMOS opamp having large sinking and sourcing currents, and capable of driving high capacitive loads. The CMOS opamp improves a prior art OPAMP that includes a folded cascode gain stage and a class A/B output stage. By inserting a source follower stage between the folded cascode stage and the output stage, the opamp can drive very large capacitive loads that can also compensate the opamp. By further modifying the output stage, the ability to sink load current is vastly improved.
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