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Jason L Copenhaver, 45300 N 137Th St UNIT A, Seattle, WA 98133

Jason Copenhaver Phones & Addresses

300 N 137Th St APT A, Seattle, WA 98133   

380 Bearded Oaks Cir, Sarasota, FL 34232    941-3780223   

3252 Wilkinson Rd, Sarasota, FL 34231    941-3780223   

3002 23Rd St, Bradenton, FL 34205    941-7452526   

Sheboygan, WI   

3002 23Rd Ave W, Bradenton, FL 34205    863-4433272   

Work

Position: Protective Service Occupations

Education

Degree: High school graduate or higher

Mentions for Jason L Copenhaver

Jason Copenhaver resumes & CV records

Resumes

Jason Copenhaver Photo 27

Software Architect At Accusoft Pegasus

Location:
Sarasota, Florida Area
Industry:
Computer Software
Jason Copenhaver Photo 28

Staff Software Engineer, Product Security

Location:
Seattle, WA
Industry:
Computer Software
Work:
iSEC Partners - Greater Seattle Area since Mar 2013
Senior Security Engineer
Accusoft Pegasus May 2010 - Feb 2013
Software Architect
Accusoft Pegasus May 2007 - May 2010
Senior Software Engineer
JDSU (formerly Acterna) Mar 2005 - May 2007
Software Engineer III
Standard Analytics, LLC Nov 2004 - Mar 2005
Software Engineer
Honeywell Sep 2003 - Nov 2004
Systems Engineer III
Acterna May 1999 - Sep 2003
Software Engineer II
Education:
University of South Florida 2003 - 2006
BA, Mathematics
University of South Florida 1999 - 2001
BS, Computer Science
Skills:
C++, Linux, C, Debugging, Python, C#, Device Drivers, Win32 Api, .Net, Software Development, Perforce, Testing, Windows Internals, Subversion, Tcp/Ip, Windbg, Visual C++, Web Services, Visual Studio, X86 Assembly, Performance Tuning, Multithreading, C++/Cli, Security, Software Engineering, Gnu Debugger, Gnu Make, Visual C#, Crash Dump Analysis, X86_64, Mac Os X, Open Source, Information Security, Java, Os X, Software Design, Penetration Testing, Vulnerability Research
Certifications:
Mcts: Windows Internals (70-660)
Microsoft
Jason Copenhaver Photo 29

Jason Copenhaver

Jason Copenhaver Photo 30

Jason Copenhaver

Publications & IP owners

Us Patents

Message Translation Systems And Methods

US Patent:
7739696, Jun 15, 2010
Filed:
Sep 8, 2005
Appl. No.:
11/222211
Inventors:
Jeffrey M. Wolfe - Parrish FL, US
Jason L. Copenhaver - Sarasota FL, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
G06F 13/00
G06F 9/45
G06F 17/00
US Classification:
719328, 717136, 717137, 717140, 717143, 715236, 715239, 715249
Abstract:
Message translation systems and methods are provided. In one embodiment, a method for translating messages comprises reading a first sequence of one or more message elements from a first interface, wherein the message elements are structured based on a first protocol; converging on a message mapping node based on the first sequence of one or more message elements, wherein the message mapping node is defined by a protocol metadata schema; performing one or more conversion operations on the first sequence of one or more message elements to construct a second sequence of one or more message elements, wherein the one or more conversion operations are based on the message mapping node; and writing the second sequence of one or more message elements to a second interface.

Method And System For Environmentally Adaptive Fault Tolerant Computing

US Patent:
7840852, Nov 23, 2010
Filed:
Aug 12, 2005
Appl. No.:
11/202467
Inventors:
Jason L. Copenhaver - Sarasota FL, US
Ramos Jeremy - Clearwater FL, US
Jeffrey M. Wolfe - Parrish FL, US
Dean Brenner - Largo FL, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
G06F 11/00
US Classification:
714 47, 714 10
Abstract:
A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based in part on the measured environmental condition. The fault tolerance of the on-board processing system may be reconfigured based in part on the measured environmental condition.

Redundant Processing Architecture For Single Fault Tolerance

US Patent:
2005027, Dec 15, 2005
Filed:
Jun 15, 2004
Appl. No.:
10/867894
Inventors:
Jeffrey Wolfe - Bradenton FL, US
Jason Copenhaver - Sarasota FL, US
Jeremy Ramos - Cleanwater FL, US
International Classification:
G06F011/00
US Classification:
714011000
Abstract:
An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.

System And Method For Dynamically Optimizing Performance And Reliability Of Redundant Processing Systems

US Patent:
2006023, Oct 19, 2006
Filed:
Apr 1, 2005
Appl. No.:
11/096872
Inventors:
Jeffrey Wolfe - Parrish FL, US
Jason Copenhaver - Sarasota FL, US
Jeremy Ramos - Clearwater FL, US
Assignee:
HONEYWELL INTERNATIONAL INC. - MORRISTOWN NJ
International Classification:
G01R 31/28
US Classification:
714724000
Abstract:
An improved system and method for dynamically optimizing the performance and reliability of redundant processing systems (e.g., for use in space applications) are disclosed. As one example, a Field Programmable Gate Array (FPGA) that includes a plurality of processors is disclosed. Based on mission specific modes or environmental conditions, the processing system can dynamically and safely transition between the high performance of, for example, a general purpose, quad Symmetric Multiprocessor (SMP) and the high reliability of a redundant set of processors (e.g., Triple Modular Redundancy system). This architecture allows the use of a single FPGA with multiple processors to take advantage of the maximum processing throughput available when sufficient mission conditions are met, and can also safely transition to a lower throughput, high reliability mode when needed. In other words, at particular points during a mission, high processing capacity and throughput can be obtained at the expense of reliability or dependability as the mission conditions allow. If the mission conditions can support a reduced level of dependability at a particular point in time, then the processors can be adapted to run in a single string (e.g., triple or quad string) to produce three to four times the processing capacity of the redundant set.

Systems And Methods For Satellite Payload Application Development

US Patent:
2007006, Mar 22, 2007
Filed:
Sep 8, 2005
Appl. No.:
11/222213
Inventors:
Jeffrey Wolfe - Parrish FL, US
Jason Copenhaver - Sarasota FL, US
Jeremy Ramos - Clearwater FL, US
Assignee:
HONEYWELL INTERNATIONAL INC. - MORRISTOWN NJ
International Classification:
G06F 3/00
US Classification:
710001000
Abstract:
System and methods for satellite payload application development are provided. A method for developing embedded processing systems comprises selecting a hardware layer configuration; and developing an interfacing software stack providing services from one or more of an infrastructure services layer, a bus abstraction layer, a device abstraction layer, and a peripheral device driver layer through one or more standard function calls.

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