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Jay W Fletcher, 65Pleasanton, CA

Jay Fletcher Phones & Addresses

Pleasanton, CA   

22613 Gierson Ave, Wildomar, CA 92595    951-6099303   

Riverside, CA   

Mentions for Jay W Fletcher

Career records & work history

Lawyers & Attorneys

Jay Fletcher Photo 1

Jay Fletcher - Lawyer

ISLN:
914499198
Admitted:
1973

Jay Fletcher resumes & CV records

Resumes

Jay Fletcher Photo 50

Project Manager

Position:
CEO at PuCS / RBD Contractor Services
Location:
Norcross, Georgia
Industry:
Construction
Work:
PuCS / RBD Contractor Services since 2009
CEO
Jay Fletcher Photo 51

Jay Fletcher

Location:
United States

Publications & IP owners

Us Patents

Voltage Regulator With Multi-Level, Multi-Phase Buck Architecture

US Patent:
2023004, Feb 16, 2023
Filed:
Aug 29, 2022
Appl. No.:
17/823027
Inventors:
- Cupertino CA, US
Jay B. Fletcher - Sunnyvale CA, US
International Classification:
H02M 3/158
Abstract:
A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

Dual Loop Ldo Voltage Regulator

US Patent:
2021008, Mar 25, 2021
Filed:
Sep 25, 2019
Appl. No.:
16/583008
Inventors:
- Cupertino CA, US
Jay B. Fletcher - Sunnyvale CA, US
Nathan F. Hanagami - San Francisco CA, US
International Classification:
G05F 1/575
G05F 1/59
Abstract:
A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.

Constant Off-Time Control Method For Buck Converters Using Coupled Inductors

US Patent:
2018008, Mar 22, 2018
Filed:
Jan 11, 2017
Appl. No.:
15/403255
Inventors:
- Cupertino CA, US
Fabio Gozzini - San Jose CA, US
Jay B. Fletcher - Austin TX, US
Shawn Searles - Austin TX, US
International Classification:
H02M 3/158
H02M 1/08
Abstract:
A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.

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