Career records & work history
Medicine Doctors
Jay A Gupta, 555000 Macarthur Blvd, Oakland, CA 94613
Jay Gupta Phones & Addresses
Oakland, CA
San Francisco, CA
New York, NY
Edison, NJ
Brooklyn, NY
2009 85Th St, Brooklyn, NY 11214
Work
Position:
Machine Operators, Assemblers, and Inspectors Occupations
Education
Degree:
Associate degree or higher
Mentions for Jay A Gupta
Jay Gupta resumes & CV records
Resumes
Assistant Professor At Mills College
Position:
Assistant Professor at Mills College
Location:
San Francisco Bay Area
Industry:
Higher Education
Work:
Mills College
since Aug 2007
Assistant Professor
Assistant Professor
Education:
University of Toronto 2001
Ph.D., Philosophy State University of New York College at Purchase
B.A., Philosophy
Ph.D., Philosophy State University of New York College at Purchase
B.A., Philosophy
Jay Gupta
Location:
United States
Abc At Abc
Position:
abc at abc
Location:
United States
Industry:
Aviation & Aerospace
Work:
abc
abc
abc
Market Research At Symantec
Position:
Market Research at Symantec
Location:
San Francisco Bay Area
Industry:
Research
Work:
Symantec
Market Research
Market Research
Jay Gupta
Location:
San Francisco Bay Area
Industry:
Semiconductors
Publications & IP owners
Us Patents
Fifo Memory System And Method
US Patent:
6948030, Sep 20, 2005
Filed:
Sep 4, 2002
Appl. No.:
10/234680
Inventors:
Jay Kishora Gupta - Sunnyvale CA, US
Amitabha Banerjee - San Jose CA, US
Somnath Paul - Fremont CA, US
Amitabha Banerjee - San Jose CA, US
Somnath Paul - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F013/00
US Classification:
711109, 711 5, 711154, 711170, 710 53, 710 57, 365 78, 36518903, 370232
Abstract:
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
Method And Apparatus For Re-Accessing A Fifo Location
US Patent:
6957309, Oct 18, 2005
Filed:
Dec 18, 2002
Appl. No.:
10/324308
Inventors:
Jay K. Gupta - Sunnyvale CA, US
Somnath Paul - Fremont CA, US
Somnath Paul - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F012/02
US Classification:
711154, 711109, 711110, 711155, 711156
Abstract:
In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.
Method Of Maximizing Bandwidth Efficiency In A Protocol Processor
US Patent:
7496109, Feb 24, 2009
Filed:
Feb 11, 2004
Appl. No.:
10/777286
Inventors:
Jay K. Gupta - Sunnyvale CA, US
Somnath Paul - Fremont CA, US
Somnath Paul - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H04L 12/56
US Classification:
370413, 370428
Abstract:
A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.
Configurable And Memory Architecture Independent Memory Built-In Self Test
US Patent:
2002013, Sep 19, 2002
Filed:
Mar 19, 2001
Appl. No.:
09/812109
Inventors:
Jay Gupta - Fremont CA, US
Somnath Paul - Milpitas CA, US
Somnath Paul - Milpitas CA, US
Assignee:
CYPRESS SEMICONDUCTOR CORP.
International Classification:
G11C029/00
US Classification:
714/719000
Abstract:
A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.
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