Jaynal A Molla, 72897 Laredo Ave, Gilbert, AZ 85233

6362089, Mar 26, 2002

Apr 19, 1999

09/294060

Jaynal Abedin Molla - Gilbert AZ
Owen Richard Fay - Chandler AZ

Motorola, Inc. - Schaumburg IL

H01L 2144

438612, 438677, 438678, 438687, 427 98, 427125, 427304, 427405, 427437, 106 123

A semiconductor wafer having copper bondpads ( ) that are free of voids ( ) and a method for coating the copper bondpads ( ) with solderable or wirebondable metals such that the copper bondpads ( ) are free of the voids ( ). The void free metal coatings are achieved using a dual activation process. In a first activation step ( ), the copper bondpads ( ) are activated by placing them in a palladium bath. In a second activation step ( ), the bondpads are placed in a nickel-boron bath. After the dual activation, the copper bondpads ( ) are coated with a layer of nickel-phosphorous or palladium. The nickel-phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.

6414509, Jul 2, 2002

May 3, 2000

09/564652

Anilkumar Chinuprasad Bhatt - Johnson City NY
Leo Raymond Buda - Vestal NY
Robert Douglas Edwards - Binghamton NY
Paul Joseph Hart - Endicott NY
Anthony Paul Ingraham - Endicott NY
Voya Rista Markovich - Endwell NY
Jaynal Abedin Molla - Endicott NY
Richard Gerald Murphy - Binghamton NY
George Frederick Walker - New York NY
Bette Jaye Whalen - Vestal NY
Richard Stuart Zarr - Apalachin NY

International Business Machines Corporation - Armonk NY

G01R 3102

324765, 324760, 324754

A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

6517698, Feb 11, 2003

Oct 6, 2000

09/680871

Timothy L. Johnson - Tempe AZ
Douglas G. Mitchell - Tempe AZ
Jaynal Abedin Molla - Gilbert AZ

Motorola, Inc. - Schaumburg IL

C25D 520

205148, 205149, 205157

A system for electroplating integrated circuit wafers includes an electroplating solution containment chamber having a first end that is capable of supporting an integrated circuit wafer so that a surface of the wafer faces an internal volume of the chamber, and a second end opposing the first end across the internal volume. The system further includes a liquid directing element at the second end. The liquid directing element includes a plurality of channels having divergent axes so as to direct a helical flow of electroplating solution toward the surface of the integrated circuit wafer when the wafer is present and the liquid directing element is attached to a source of pressurized electroplating solution.

6885074, Apr 26, 2005

Nov 27, 2002

10/306250

Mark A. Durlam - Chandler AZ, US
Jeffrey H. Baker - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark F. Deherrera - Tempe AZ, US
John J. D'Urso - Chandler AZ, US
Earl D. Fuchs - Phoenix AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Kelly W. Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Nicholas D. Rizzo - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L029/82
H01L027/14

257422, 257252

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

6927072, Aug 9, 2005

Mar 8, 2002

10/093909

Jaynal A. Molla - Gilbert AZ, US
John D'Urso - Chandler AZ, US
Kelly Kyler - Mesa AZ, US
Bradley N. Engel - Chandler AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Nicholas D. Rizzo - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L021/00

438 3, 438612, 438613, 438614, 257295, 365158, 365171, 365172, 365173

A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

6936763, Aug 30, 2005

Jun 28, 2002

10/184536

Nicholas D. Rizzo - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US
Michael J. Roll - Scottsdale AZ, US
Kelly Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01B011/00

174 35R, 174 35 MS, 174 33, 205118, 205119, 361816, 361818

Shielded electronic integrated circuit apparatus () includes a substrate (), with an eletronic integrated circuit () formed thereon, and a dielectric region () positioned on the electronic integrated circuit. The dielectric region and the substrate are substantially surrounded by lower and upper magnetic material regions (), deposited using electrochemical deposition, and magnetic material layers on each side (). Each of the lower and upper magnetic material regions preferably include a glue layer (), a seed layer (), and an electrochemically deposited magnetic material layer (). Generally, the electrochemically deposited magnetic material layer can be conveniently deposited by electroplating.

6943038, Sep 13, 2005

Dec 19, 2002

10/324716

Thomas V. Meixner - Gilbert AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Richard G. Williams - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L021/00

438 3, 438692, 438238

A method for fabricating a flux concentrating system () for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line () formed in a substrate () and forming a first material layer () overlying the bit line () and the substrate (). Etching is performed to form a trench () in the first material layer () and a cladding layer () is deposited in the trench (). A buffer material layer () is formed overlying the cladding layer () and a portion of the buffer material layer () and a portion of the cladding layer () is removed.

7105363, Sep 12, 2006

Mar 16, 2005

11/082617

Mark A. Durlam - Chandler AZ, US
Jeffrey H. Baker - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark F. Deherrera - Tempe AZ, US
John J. D'Urso - Chandler AZ, US
Earl D. Fuchs - Phoenix AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Kelly W. Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Nicholas D. Rizzo - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438 3, 438652, 438653, 438666, 257E21002

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().