Jeffrey Brooks, 692474 S 17000 Rd, Reddick, IL 60961

6460134, Oct 1, 2002

Oct 28, 1998

09/181406

James S. Blomgren - Austin TX
Terence M. Potter - Austin TX
Jeffrey S. Brooks - Round Rock TX

Intrinsity, Inc. - Austin TX

G06F 930

712219

The present invention comprises a method and apparatus for a pipeline of functional units with a late pipe functional unit that executes instructions without stalling until the result is available. The present invention comprises one or more earlier functional units coupled to a late pipe functional unit. The late pipe functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that the late pipe functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles. The present invention further comprises a late pipe functional unit that may comprise a floating point unit, a graphics unit, or an enhanced floating point unit. And finally, the late pipe functional unit is non-stalling and or is non-cancelable.

6499044, Dec 24, 2002

Apr 10, 2000

09/546412

Jeffrey S. Brooks - Austin TX, 78733
James S. Blomgren - Austin TX, 78701
David E. Kreml - Spicewood TX, 78669

G06F 750

708211, 708205

An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.

6567835, May 20, 2003

Sep 17, 1999

09/398618

James S. Blomgren - Austin TX
Jeffrey S. Brooks - Round Rock TX

Intrinsity, Inc. - Austin TX

G06F 750

708708, 708493

The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I , I , I , I and I and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T , T , and T. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.

6557021, Apr 29, 2003

Mar 17, 2000

09/527653

Jeffrey S. Brooks - Austin TX
James S. Blomgren - Austin TX

Intrinsity, Inc. - Austin TX

G06F 738

708496, 708551, 708493

A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.

7099910, Aug 29, 2006

Apr 7, 2003

10/408132

Jeffrey S. Brooks - Austin TX, US
Christopher H. Olson - Austin TX, US
Paul J. Jagodik - Austin TX, US

Sun Microsystems, Inc. - Palo Alto CA

G06F 7/485

708505

A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.

7216216, May 8, 2007

Jun 30, 2004

10/881556

Christopher H. Olson - Austin TX, US
Jeffrey S. Brooks - Austin TX, US
Robert T. Golla - Round Rock TX, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

712220

In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.

7373489, May 13, 2008

Jun 30, 2004

10/880713

Jeffrey S. Brooks - Austin TX, US
Paul J. Jordan - Austin TX, US
Rabin A. Sugumar - Sunnyvale CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 9/00
G06F 7/38
G06F 9/44

712244, 708498, 708495, 712222

An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.

7433912, Oct 7, 2008

Feb 19, 2004

10/782162

Paul J. Jagodik - Austin TX, US
Jeffrey S. Brooks - Austin TX, US
Christopher Olson - Austin TX, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 7/533

708628

A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is partitionable having a plurality of sub-trees. The multiplier is configured to be a single tree structure in response to a non-SIMD multiplication instruction and as a partitioned tree structure in response to a SIMD multiplication instruction. At least two multiplication operations can be performed in parallel in the partitioned tree structure in response to the SIMD multiplication instruction and a single multiplication operation is performed in the single tree structure in response to the non-SIMD multiplication instruction. Appropriate formatting of the input operands and selection of data from the tree structures is performed in accordance with the instruction.