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Jeffrey S Leal, 47Murrieta, CA

Known as:
Jeffrey Steve Leal Jeff S Leal
Related to:
Irma Susana Hernandez

Jeffrey Leal Phones & Addresses

Murrieta, CA   

93 Brett Ave, Tracy, CA 95391    209-8345709   

Mountain House, CA   

Scotts Valley, CA   

Carlsbad, CA   

Mount Laurel, NJ   

Winchester, CA   

26432 Arboretum Way UNIT 904, Murrieta, CA 92563   

Work

Position: Craftsman/Blue Collar

Education

Degree: High school graduate or higher
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Jeffrey Leal resumes & CV records

Resumes

Jeffrey Leal Photo 27

Jeffrey Leal

Work:
TURLOCK IRRIGATION DISTRICT Oct 2004 to 2000
Sr. Network Engineer / DBA THE DIMARE COMPANY - Newman, CA Mar 1998 to Oct 2004
Network Administrator NORTH AMERICAN MEDICAL MANAGEMENT - Modesto, CA May 1997 to Dec 1997
MIS Network Technician/ Assistant Network Administrator
Education:
UNIVERSITY OF THE PACIFIC - Stockton, CA Aug 1997
Bachelor of Science in Computer Information Systems
Jeffrey Leal Photo 28

Jeffrey Leal - Scotts Valley, CA

Work:
Vertical Circuits Incorporated 2007 to 2000
Engineering Manager Nordson Asymtek - Carlsbad, CA 1997 to 2007
Application Engineer/Senior Field Service Engineer
Education:
Universidad Latina de Costa Rica 2004
B.S. in Electronics Engineering
Skills:
Performance Based Equipment Training (PBET), JMP, Numerous Lean Manufacturing and Design Workshops

Publications & IP owners

Wikipedia

Jeffrey Leal Photo 29

Jeff Leal

Jeff Leal (born 1954 in Peterborough, Ontario) is a politician in Ontario, Canada. He is currently a member of the Legislative Assembly of Ontario, ...

Us Patents

Flat Leadless Packages And Stacked Leadless Package Assemblies

US Patent:
8159053, Apr 17, 2012
Filed:
Sep 28, 2010
Appl. No.:
12/892739
Inventors:
Jeffrey S. Leal - Scotts Valley CA, US
Simon J. S. McElrea - Scotts Valley CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 23/495
US Classification:
257676, 257666, 257E23037
Abstract:
A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Electrical Interconnect Formed By Pulsed Dispense

US Patent:
2009006, Mar 12, 2009
Filed:
May 20, 2008
Appl. No.:
12/124097
Inventors:
Terrence Caskey - Santa Cruz CA, US
Simon J.S. McElrea - Scotts Valley CA, US
Scott McGrath - Scotts Valley CA, US
Jeffrey S. Leal - Santa Cruz CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 21/60
H01L 21/44
US Classification:
438109, 438618, 257E21506, 257E21476
Abstract:
Methods for depositing interconnect material at a target for electrical interconnection include pulsed dispense of the material. In some embodiments droplets of interconnect material are deposited in a projectile fashion. In some embodiments the droplets are shaped by movement of the deposition tool following a deposition pulse and prior to separation of the droplet mass from the tool.

Flat Leadless Packages And Stacked Leadless Package Assemblies

US Patent:
2009020, Aug 20, 2009
Filed:
Aug 27, 2008
Appl. No.:
12/199667
Inventors:
JEFFREY S. LEAL - Santa Cruz CA, US
SIMON J.S. McELREA - Scotts Valley CA, US
Assignee:
VERTICAL CIRCUITS, INC. - SCOTTS VALLEY CA
International Classification:
H01L 23/495
US Classification:
257676, 257E23037
Abstract:
A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Semiconductor Die Interconnect Formed By Aerosol Application Of Electrically Conductive Material

US Patent:
2010014, Jun 10, 2010
Filed:
Dec 9, 2009
Appl. No.:
12/634598
Inventors:
Jeffrey S. Leal - Scotts Valley CA, US
Scott McGrath - Scotts Valley CA, US
Suzette K. Pangrle - Cupertino CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 23/52
H01L 21/50
US Classification:
257777, 438107, 257E21499, 257E23141
Abstract:
An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.

Electrical Interconnect For Die Stacked In Zig-Zag Configuration

US Patent:
2010032, Dec 30, 2010
Filed:
Jun 23, 2010
Appl. No.:
12/821454
Inventors:
Reynaldo Co - Scotts Valley CA, US
Grant Villavicencio - Scotts Valley CA, US
Jeffrey S. Leal - Scotts Valley CA, US
Simon J.S. McElrea - Scotts Valley CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 25/065
H01L 21/60
H01L 21/77
H01L 23/538
US Classification:
257777, 438107, 257E21506, 257E21598, 257E23169, 257E25013
Abstract:
A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate.

Selective Die Electrical Insulation By Additive Process

US Patent:
2011026, Nov 3, 2011
Filed:
Oct 27, 2010
Appl. No.:
12/913529
Inventors:
Jeffrey S. Leal - Scotts Valley CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 21/28
H01L 21/31
H01L 23/48
H01L 21/768
US Classification:
257773, 438674, 438109, 438778, 257E21158, 257E21575, 257E2124, 257E2301
Abstract:
Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

Stacked Die Assembly Having Reduced Stress Electrical Interconnects

US Patent:
2011027, Nov 10, 2011
Filed:
Nov 4, 2010
Appl. No.:
12/939524
Inventors:
Scott McGrath - Scotts Valley CA, US
Jeffrey S. Leal - Scotts Valley CA, US
Ravi Shenoy - Dublin CA, US
Loreto Cantillep - San Jose CA, US
Simon J. S. McElrea - Scotts Valley CA, US
Suzette K. Pangrle - Cupertino CA, US
Assignee:
Vertical Circuits, Inc. - Scotts Valley CA
International Classification:
H01L 23/522
H01L 21/56
US Classification:
257777, 438124, 257E23142, 257E21503
Abstract:
Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Electrical Connector Between Die Pad And Z-Interconnect For Stacked Die Assemblies

US Patent:
2012011, May 17, 2012
Filed:
May 17, 2011
Appl. No.:
13/109996
Inventors:
Reynaldo Co - Scotts Valley CA, US
Jeffrey S. Leal - Scotts Valley CA, US
Suzette K. Pangrle - Cupertino CA, US
Scott McGrath - Scotts Valley CA, US
DeAnn Elleen Melcher - San Jose CA, US
Keith L. Barrie - Capitola CA, US
Grant Villavicencio - Scotts Valley CA, US
Elmer M. del Rosario - San Jose CA, US
John R. Bray - San Jose CA, US
Assignee:
VERTICAL CIRCUITS, INC. - Scotts Valley CA
International Classification:
H01L 23/52
H01L 21/78
US Classification:
257777, 438462, 257E21599, 257E23141
Abstract:
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Possible Relatives

Cynthia V Leal  David Leal  Daisy Leal  Dalia Leal  Damian A Leal  Deborah L Leal  Daniel Leal  Jeffrey P Johnson  Jeffrey Stamps  Jeffrey Standard 

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