Jeffrey S Leib, 444637 NW Woodside Ter, Portland, OR 97210

2021009, Mar 25, 2021

Nov 20, 2020

17/100689

- Santa Clara CA, US
Steven JALOVIAR - Banks OR, US
Jeffrey S. LEIB - Beaverton OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/78
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 23/522
H01L 23/532
H01L 29/165
H01L 29/417
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

2020038, Dec 10, 2020

Aug 24, 2020

17/000615

- Santa Clara CA, US
Steven JALOVIAR - Hillsboro OR, US
Jeffrey S. LEIB - Beaverton OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/78
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 23/522
H01L 23/532
H01L 29/165
H01L 29/417
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

2020006, Feb 27, 2020

Sep 30, 2016

16/324087

- Santa Clara CA, US
Jeffrey S. LEIB - Hillsboro OR, US
Michael L. MCSWINEY - Scappoose OR, US
Harsono S. SIMKA - Saratoga CA, US
Daniel B. BERGSTROM - Lake Oswego OR, US

Intel Corporation - Santa Clara CA

H01L 23/532
H01L 21/285
H01L 21/768
H01L 23/522

Embodiments of the invention include a microelectronic device that includes a substrate having a layer of dielectric material that includes a feature with a depression, a Tungsten containing barrier liner layer formed in the depression of the feature, and a Cobalt conductive layer deposited on the Tungsten containing barrier liner layer in the depression of the feature. The Tungsten containing barrier liner layer provides adhesion for the Cobalt conductive layer.

2020002, Jan 23, 2020

Jul 11, 2019

16/509395

- Santa Clara CA, US
Jeffrey S. LEIB - Beaverton OR, US
Michael L. HATTENDORF - Portland OR, US

H01L 29/66
H01L 21/768
H01L 29/78
H01L 29/417
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 23/522
H01L 23/532
H01L 29/165
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

2019016, May 30, 2019

Dec 30, 2017

15/859410

- Santa Clara CA, US
Jeffrey S. LEIB - Beaverton OR, US
Michael L. HATTENDORF - Portland OR, US

H01L 29/66
H01L 29/78
H01L 21/8234

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

2019016, May 30, 2019

Oct 25, 2018

16/170600

- Santa Clara CA, US
Steven JALOVIAR - Hillsboro OR, US
Jeffrey S. LEIB - Beaverton OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/06
H01L 29/78
H01L 27/088
H01L 21/8234
H01L 21/762

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

2017027, Sep 28, 2017

Jun 9, 2017

15/619283

- Santa Clara CA, US
JEFFREY S. LEIB - Hillsboro OR, US
DANIEL B. BERGSTROM - Lake Oswego OR, US

Intel Corporation - Santa Clara CA

H01L 21/768
H01L 21/28
H01L 23/528
H01L 23/532
H01L 21/285
H01L 29/51

An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

2016030, Oct 20, 2016

Dec 26, 2013

15/100531

Jason A Farmer - Hillsboro OR, US
Jeffrey S Leib - Hillsboro OR, US
Daniel B Bergstrom - Santa Clara CA, US

INTEL CORPORATION - Santa Clara CA

H01L 21/768
H01L 23/532
H01L 23/528

An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.