Jeffrey C Maling, 9322 Moccasin Ave, Point Farm, VT 05458

7101806, Sep 5, 2006

Oct 15, 2004

10/711953

June Cline - South Burlington VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Colchester VT, US
Jeffrey C. Maling - Grand Isle VT, US
Lisa Y. Ninomiya - Ridgefield CT, US
Bruce W. Porth - Jericho VT, US
Steven M. Shank - Jericho VT, US
Jessica A. Trapasso - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 21/302

438724, 438700, 438719, 438723, 438736, 438739, 438952

A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.

7573085, Aug 11, 2009

Jul 20, 2006

11/458828

June Cline - South Burlington VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Colchester VT, US
Jeffrey C. Maling - Grand Isle VT, US
Lisa Y. Ninomiya - Ridgefield CT, US
Bruce W. Porth - Jericho VT, US
Steven M. Shank - Jericho VT, US
Jessica A. Trapasso - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 27/108

257296, 438736, 438739, 257E21035, 257E21023

A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

7893479, Feb 22, 2011

Aug 10, 2009

12/538193

June Cline - Essex Junction VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Essex Junction VT, US
Jeffrey C. Maling - Essex Junction VT, US
Lisa Y. Ninomiya - Essex Junction VT, US
Bruce W. Porth - Essex Junction VT, US
Steven M. Shank - Essex Junction VT, US
Jessica A. Trapasso - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 29/108

257296, 257E21035, 257E21023, 438736

A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

2006012, Jun 15, 2006

Dec 13, 2004

10/905043

James Adkisson - Jericho VT, US
Mark Jaffe - Shelburne VT, US
Arthur Johnson - Essex Junction VT, US
Robert Leidy - Burlington VT, US
Jeffrey Maling - Grand Isle VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 21/425

438525000

A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.

2011031, Dec 29, 2011

Dec 21, 2010

12/974854

Dinh DANG - Essex Junction VT, US
Thai DOAN - Burlington VT, US
Zhong-Xiang HE - Essex Junction VT, US
Russell T. HERRIN - Essex Junction VT, US
Christopher V. JAHNES - Upper Saddle River NJ, US
Jeffrey C. MALING - Grand Isle VT, US
William J. MURPHY - North Ferrisburgh VT, US
Anthony K. STAMPER - Williston VT, US
John G. TWOMBLY - Essex Junction VT, US
Eric J. WHITE - Charlotte VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01H 57/00
H01L 21/66
G06F 17/50
H01L 21/28

200181, 438667, 438 14, 716110, 257E21158, 257E21529

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

2011031, Dec 29, 2011

Dec 23, 2010

12/977850

Russell T. HERRIN - Essex Junction VT, US
Jeffrey C. Maling - Grand Isle VT, US
Anthony K. Stamper - Williston VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01H 57/00
G06F 17/50
H01L 21/56

200181, 438127, 716 55, 257E21502

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

2011031, Dec 29, 2011

Dec 20, 2010

12/973333

Jeffrey C. MALING - Grand Isle VT, US
William J. MURPHY - North Ferrisburgh VT, US
Anthony K. STAMPER - Williston VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/84
H01L 21/02

257415, 438 50, 257E21002, 257E29324

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower sacrificial material used to form a lower cavity. The method further includes forming a cavity via connecting the lower cavity to an upper cavity. The cavity via is formed with a top view profile of rounded or chamfered edges. The method further includes forming an upper sacrificial material within and above the cavity via, which has a resultant surface based on the profile of the cavity via. The upper cavity is formed with a lid that is devoid of structures that would interfere with a MEMS beam, including: depositing a lid material on the resultant surface of the upper sacrificial material; and venting the upper sacrificial material to form the upper cavity such the lid material forms the lid which conforms with the resultant surface of the upper sacrificial material.

2011031, Dec 29, 2011

Dec 20, 2010

12/973422

Zhong-Xiang HE - Essex Junction VT, US
Jeffrey C. MALING - Grand Isle VT, US
William J. MURPHY - North Ferrisburgh VT, US
Anthony K. STAMPER - Williston VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/84
H01L 21/02

257415, 438 50, 257E29324, 257E21002

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.