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Jeffrey C Munro, 47Bellaire, TX

Jeffrey Munro Phones & Addresses

Bellaire, TX   

6315 Mystic St, Houston, TX 77021    713-7471400   

Santa Clara, CA   

Williamsburg, VA   

Palo Alto, CA   

Boston, MA   

Herndon, VA   

106 Royal Worlington, Williamsburg, VA 23188    757-5640189   

Mentions for Jeffrey C Munro

Career records & work history

Medicine Doctors

Jeffrey A. Munro

Specialties:
Anesthesiology
Work:
Johnson County Anesthesia
20333 W 151 St, Olathe, KS 66061
913-7822292 (phone) 913-7822381 (fax)
Site
Education:
Medical School
University of Nebraska College of Medicine
Graduated: 1992
Languages:
English, Spanish
Description:
Dr. Munro graduated from the University of Nebraska College of Medicine in 1992. He works in Olathe, KS and specializes in Anesthesiology. Dr. Munro is affiliated with Olathe Medical Center.

License Records

Jeffrey Adrian Munro Md

Licenses:
License #: 1601 - Expired
Category: Medicine
Issued Date: Jun 9, 1997
Effective Date: Oct 2, 1997
Type: Backup PA Supervisor

Jeffrey Adrian Munro Md

Licenses:
License #: 19208 - Expired
Category: Medicine
Issued Date: Jul 15, 1993
Effective Date: Nov 24, 1998
Expiration Date: Oct 1, 1998
Type: Physician

Jeffrey Adrian Munro Md

Licenses:
License #: 2856 - Expired
Category: Medicine
Issued Date: Jul 1, 1992
Effective Date: Jul 15, 1993
Type: Temporary Educational Permit

Publications & IP owners

Wikipedia

Jeffrey Munro Photo 13

Fileedmt Downtown Panoramic.jpg The Free ...

English: Cityscape of Edmonton, Alberta. January 2009. Date. 10/01/09. Source. My Own. Author. Jeffrey Munro. Permission (Reusing this file). See below. ...

Us Patents

Formation Of High Quality Dielectric Films Of Silicon Dioxide For Sti: Usage Of Different Siloxane-Based Precursors For Harp Ii—Remote Plasma Enhanced Deposition Processes

US Patent:
7498273, Mar 3, 2009
Filed:
Oct 16, 2006
Appl. No.:
11/549930
Inventors:
Abhijit Basu Mallick - Palo Alto CA, US
Jeffrey C. Munro - Santa Clara CA, US
Srinivas D. Nemani - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438931, 438753, 257E2117, 257E21277, 257E21278, 257E21311, 257E21304
Abstract:
Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.

Method And System For Improving Dielectric Film Quality For Void Free Gap Fill

US Patent:
7541297, Jun 2, 2009
Filed:
Oct 22, 2007
Appl. No.:
11/876541
Inventors:
Abhijit Basu Mallick - Palo Alto CA, US
Jeffrey C. Munro - Houston TX, US
Linlin Wang - San Jose CA, US
Srinivas D. Nemani - Sunnyvale CA, US
Yi Zheng - San Jose CA, US
Zheng Yuan - Fremont CA, US
Dimitry Lubomirsky - Cupertino CA, US
Ellie Y. Yieh - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/469
H01L 21/31
US Classification:
438778, 438758, 438770, 438773, 438787, 257E21279, 257E21576
Abstract:
A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.

Post Deposition Plasma Treatment To Increase Tensile Stress Of Hdp-Cvd Sio

US Patent:
7745351, Jun 29, 2010
Filed:
Oct 15, 2008
Appl. No.:
12/252260
Inventors:
Xiaolin Chen - San Jose CA, US
Srinivas D. Nemani - Sunnyvale CA, US
DongQing Li - Fremont CA, US
Jeffrey C. Munro - Santa Clara CA, US
Marlon E. Menezes - Mountain View CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/31
H01L 21/469
US Classification:
438788, 438782, 438798, 257E21241
Abstract:
Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

Method For Depositing And Curing Low-K Films For Gapfill And Conformal Film Applications

US Patent:
7790634, Sep 7, 2010
Filed:
May 25, 2007
Appl. No.:
11/753918
Inventors:
Jeffrey C. Munro - Santa Clara CA, US
Srinivas D. Nemani - Sunnyvale CA, US
Assignee:
Applied Materials, Inc - Santa Clara CA
International Classification:
H01L 21/31
H01L 21/469
US Classification:
438789, 438794, 438793, 257E21489, 257E21493, 257E21478
Abstract:
Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is generated outside the reaction chamber. The methods also include heating the silicon oxide layer at a temperature of about 600 C. or less, and exposing the silicon oxide layer to an induced coupled plasma. Additional methods are described where the deposited silicon oxide layer is cured by exposing the layer to ultra-violet light, and also exposing the layer to an induced coupled plasma.

Dopant Activation In Doped Semiconductor Substrates

US Patent:
7989366, Aug 2, 2011
Filed:
Aug 24, 2007
Appl. No.:
11/844810
Inventors:
Jeffrey C. Munro - Santa Clara CA, US
Srinivas D. Nemani - Sunnyvale CA, US
Young S. Lee - San Jose CA, US
Marlon Menezes - Mountain View CA, US
Christopher Dennis Bencher - San Jose CA, US
Vijay Parihar - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438795, 438142, 438162, 438308, 438478, 438510, 438584, 438780, 438781
Abstract:
Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500 C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0. 3 at a wavelength comprised by the electromagnetic radiation.

Polymer Pi-Bond-Philic Filler Composites

US Patent:
8343257, Jan 1, 2013
Filed:
Nov 20, 2009
Appl. No.:
12/623355
Inventors:
Scott T. Matteucci - Midland MI, US
Shawn D. Feist - Midland MI, US
Peter N. Nickias - Midland MI, US
Leonardo C. Lopez - Midland MI, US
Michael S. Paquette - Midland MI, US
Jeffrey C. Munro - Houston TX, US
Assignee:
Dow Global Technologies LLC - Midland MI
International Classification:
B01D 53/22
B01D 71/02
B01D 71/06
C08J 5/22
US Classification:
95 45, 95 50, 95 52, 96 4, 96 9, 96 11, 96 12, 521 25, 521 27, 25251933, 502439
Abstract:
The instant invention generally provides polymer pi-bond-philic filler composite comprising a molecularly self-assembling material and a pi-bond-philic filler, and a process of making and an article comprising the polymer pi-bond-philic filler composite. The instant invention also generally provides a process of separating a pi-bond-philic gas from a separable gas mixture comprising the pi-bond-philic gas.

Post Deposition Plasma Treatment To Increase Tensile Stress Of Hdp-Cvd Sio2

US Patent:
2007005, Mar 8, 2007
Filed:
Sep 7, 2005
Appl. No.:
11/221303
Inventors:
Xiaolin Chen - San Jose CA, US
Srinivas Nemani - Sunnyvale CA, US
DongQing Li - Fremont CA, US
Jeffrey Munro - Santa Clara CA, US
Marlon Menezes - Mountain View CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L 21/31
US Classification:
438787000, 257E21241
Abstract:
A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.

Olefin Block Copolymer Composition With Low Tack

US Patent:
2011030, Dec 15, 2011
Filed:
Jun 14, 2011
Appl. No.:
13/159660
Inventors:
Ashish Batra - Carmel IN, US
Jeffrey C. Munro - Houston TX, US
Jose M. Rego - Houston TX, US
Dana Breed - Lake Jackson TX, US
Pradeep Jain - Lake Jackson TX, US
Robert T. Johnston - Lake Jackson TX, US
Alec Y. Wang - Lake Jackson TX, US
Assignee:
Dow Global Technologies LLC - Midland MI
International Classification:
C08L 53/00
US Classification:
524505
Abstract:
Disclosed are oil-extended olefin block copolymer compositions with low, or no, tack. A unique comonomer content in the soft segment of the OBC in conjunction with the presence of a polyolefin provides the present oil-extended OBC composition with softness, low (or no) tack, and low (or no) oil-bleed.

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