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Jeffrey M Nguyen, 517 Treestar Pl, Spring, TX 77381

Jeffrey Nguyen Phones & Addresses

7 Treestar Pl, Spring, TX 77381    703-8626355   

The Woodlands, TX   

Vienna, VA   

Cedar Park, TX   

Rockville, MD   

Washington, DC   

Cary, NC   

Fairfax, VA   

Mentions for Jeffrey M Nguyen

Resumes & CV records

Resumes

Jeffrey Nguyen Photo 48

Directional Drilling Intern

Location:
Spring, TX
Industry:
Oil & Energy
Work:
Ryan Directional Services
Directional Drilling Intern
Education:
The University of Texas at Austin 2009 - 2014
Bachelors, Petroleum Engineering
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At And T Summer Learning Experience

Work:

At and T Summer Learning Experience
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Jeffrey Nguyen

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Jeffrey Nguyen

Jeffrey Nguyen Photo 52

Jeffrey Tung Khai Nguyen

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Jeffrey Nguyen

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Jeffrey Nguyen

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Jeffrey Nguyen

Publications & IP owners

Us Patents

Skewed Memory Cell Apparatus And Method

US Patent:
5901079, May 4, 1999
Filed:
Jan 13, 1997
Appl. No.:
8/782723
Inventors:
Tom Tien-Cheng Chiu - Austin TX
Donald George Mikan - Austin TX
Jeffrey Tuan Nguyen - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800
US Classification:
365154
Abstract:
An improved random-access memory apparatus and method for rapidly reading and writing high-level logic data to and fiom the random-access memory apparatus during phase-driven timing cycles. The improved random-access memory apparatus includes an unbalanced storage circuit for the evanescent storage of binary data, and includes two opposing logic inverters coupled together such that high level logic data can be rapidly written to the unbalanced storage circuit during a write cycle. A first logic inverter is sized larger than a second logic inverter. In addition, the improved random-access memory apparatus includes a circuit for reading and writing binary data to and from the unbalanced storage circuit. The circuit for reading and writing binary data to and from the unbalanced storage circuit operates in a cycle which includes clock phases carried on a phase line to the circuit for reading and writing binary data to and from the unbalanced storage circuit. The first logic inverter included within the unbalanced storage circuit is preferably a high-performance type of logic inverter type and the second logic inverter is preferably of a type weak in its ability to drive a binary logic signal.

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