Jeffrey A Van, 6847 Hornbeam Dr, Cranston, RI 02921

6577110, Jun 10, 2003

Jan 12, 2001

09/759064

Jeffrey B. Van Auken - Littleton MA

Sipex Corporation - Milpitas CA

G05F 140

323282, 323224, 323225, 323284

A circuit and method for powering DC devices using DC voltage sources. The present invention provides an improved switching power supply that has reduced switching losses and prevents current backflow under light load conditions. The circuit operates using pulse-frequency modulation in discontinuous conduction mode for powering small loads. A rectifier circuit prevents current backflows into the DC voltage source to prevent overheating and device failure.

5973486, Oct 26, 1999

Oct 1, 1997

8/941840

Jeffrey B. Van Auken - Littleton MA

Sipex Corporation - Billerica MA

G05F 140

323274

A power sensor circuit including an input terminal, a switch, a nonlinear voltage drop element, and a switching unit, wherein the switching unit provides an output voltage. In response to a voltage difference between a first reference voltage and a second reference voltage, the power sensor circuit outputs a voltage that varies between two states. In one embodiment, the first state is substantially equal to the second reference voltage and the second state is substantially equal to ground. In another embodiment, the power sensor circuit is composed of four metal oxide semiconductor field effect transistors (MOSFETs) that compare a first reference voltage with a second reference voltage and determine whether the second reference voltage exceeds the first reference voltage by a predetermined voltage. If so, then the second reference voltage is produced at the output terminal of the power sensor circuit. Conversely, if the second reference voltage does not exceed the first reference voltage by the same predetermined level, then the output terminal is substantially at ground.

5831562, Nov 3, 1998

Jul 12, 1996

8/678976

Jeffrey B. Van Auken - Littleton MA
Joseph L. Sousa - Lawrence MA

Sipex Corporation - Billerica MA

H03M 138

341122

A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors. Each of the common mode capacitors has an output terminal electrically coupled to a reference voltage and an input terminal electrically coupled to the input terminal of a different differential capacitor.

5638072, Jun 10, 1997

Dec 7, 1994

8/350645

Jeffrey B. Van Auken - Littleton MA
Joseph L. Sousa - Lawrence MA

Sipex Corporation - Billerica MA

H03M 100

341141

A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

5831893, Nov 3, 1998

Jul 25, 1997

8/900313

Jeffrey B. Van Auken - Littleton MA

Sipex Corporation - Billerica MA

G11C 1706

365100

A read-only memory cell capable of being programmed by the application of radiant energy. The memory cell includes a trimmable resistor, a diode and a latch. In one embodiment, the cathode of the diode is in electrical communication with a first terminal of the resistor and the anode of the diode is in electrical communication with the second terminal of the resistor. The latch has an input terminal in electrical communication with the second terminal of the resistor and an output terminal. The latch is in a first state when the trimmable resistor is untrimmed and is in a second state when the trimmable resistor is trimmed. In one embodiment, the trimmable resistor is trimmable by laser energy. The invention also relates to a method of storing data in a memory cell.

6160390, Dec 12, 2000

Jan 28, 2000

9/494326

Manuel R. Gheeraert - Nashua NH
Jeffrey B. Van Auken - Littleton MA
Alex Gusinov - Lexington MA

G05F 304

323312

A method and circuit for error current compensation is presented. The method includes the steps of generating a first current and an associated error current, generating a second current and an associated error current substantially equal to the first current and the first error current, respectively, and generating a third current substantially equal to the first current. The method includes the additional steps of extracting the second error current from the second current, generating a multiplied current equal to the scaled error current plus a multiplier error current, and combining the multiplied current with the first current and first error current. The circuit for error current compensation includes a first, second and third current source, a multiplier, and a first and second subtractor. The first subtractor provides a first difference current equal to the difference of a second current and second error current generated by the second current source and a third current generated by the third current source. The multiplier generates a predetermined multiple of the second error current and a multiplier error current at its output terminal.

2020025, Aug 13, 2020

Oct 23, 2018

16/758504

- Cambridge MA, US
Andrew Navia - Cambridge MA, US
Jeffrey F. van Humbeck - Cambridge MA, US
Marc H. Wadsworth II - Cambridge MA, US
Shaina Carroll - Cambridge MA, US
Travis K. Hughes - Cambridge MA, US

G01N 33/543
C12Q 1/6816

The present invention relates to functionalized solid supports and methods of making functionalized solid supports. Methods for preparing a population of high quality functionalized solid supports for use in various nucleic acid analysis methods are provided. The invention also provides methods for validation and quality control of the functionalization steps.

2020011, Apr 16, 2020

Mar 19, 2018

16/494911

- Cambridge MA, US
Alexander S. Genshaft - Cambridge MA, US
Carly G.K. Ziegler - Cambridge MA, US
Jeffrey F. Van Humbeck - Cambridge MA, US
Ryan Philip King - Cambridge MA, US

C12Q 1/6881
C12Q 1/6869
G01N 1/28
G16B 45/00
C07D 495/04
C07D 405/12

The present invention provides tools and methods for the systematic analysis of genetic interactions between cells. The present invention provides tools and methods for modulating cell phenotypes and compositions, combinatorial probing of cellular circuits, for dissecting cellular circuitry, for delineating molecular pathways, and/or for identifying relevant targets for therapeutics development.