Jeffrey A Wilcox, 64Chelmsford, MA

6532547, Mar 11, 2003

Jun 16, 1995

08/491467

Jeffrey A. Wilcox - Bourne MA

EMC Corporation - Hopkinton MA

H02H 305

714 5, 714 42, 714 44, 710 72, 710100

A redundant peripheral device subsystem in a computer system is disclosed including first and second peripheral device controllers. First and second peripheral device busses are coupled to the first and second peripheral device controllers, respectively. A controllable switch is coupled between the first and second peripheral device busses. The controllable switch either isolates the first and second peripheral device busses from each other, or joins them into a single peripheral device bus.

2006025, Nov 16, 2006

May 13, 2005

11/129247

Ron Swartzentruber - Amesbury MA, US
Jeffrey Wilcox - Chelmsford MA, US

H04L 12/56

370394000

An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

2007011, May 24, 2007

May 13, 2005

11/129250

Ron Swartzentruber - Amesbury MA, US
Jeffrey Wilcox - Chelmsford MA, US

G06F 13/00

710316000

An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

5886557, Mar 23, 1999

Jun 28, 1996

8/670858

Jeffrey Wilcox - Westford MA

EMC Corporation - Hopkinton MA

H03K 3013

327292

A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

5594862, Jan 14, 1997

Jul 20, 1994

8/278870

Jeffrey L. Winkler - Princeton MA
Jeffrey A. Wilcox - Bourne MA

EMC Corporation - Hopkinton MA

G06F 1100
H03M 1300

39518203

An XOR controller which is capable of performing the XOR operations necessary to generate a new parity value corresponding to new data being written to a disk storage device from a host computer without the intervention of the storage subsystem microprocessor. In one embodiment the storage subsystem microprocessor controls the loading of the new data from the host and old data and parity from a disk storage device into cache memory, if such data is not already in cache memory, and creates the appropriate data structures. The storage subsystem microprocessor then loads the XOR controller with a pointer to a table in cache memory containing information needed by the XOR controller to perform the XOR operations. The XOR controller, upon completion of the XOR operations on all the data, informs the storage subsystem microprocessor of such completion. Thereafter, the microprocessor causes the new data and new parity to be written to the disk storage device from the cache memory.

6107855, Aug 22, 2000

Sep 17, 1998

9/156747

Jeffrey Wilcox - Westford MA

EMC Corporation - Hopkinton MA

G06F 104

327295

A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

5798961, Aug 25, 1998

Aug 23, 1994

8/294481

Christopher A. Heyden - Belmont MA
Jeffrey S. Kinne - Millis MA
Mitchell N. Rosich - Groton MA
Jeffrey A. Wilcox - Bourne MA
Jeffrey L. Winkler - Princeton MA

EMC Corporation - Hopkinton MA

G11C 502

365 52

A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

5586300, Dec 17, 1996

Jul 20, 1994

8/277880

Jeffrey A. Wilcox - Bourne MA
Jeffrey L. Winkler - Princeton MA

EMC Corporation - Hopkinton MA

G06F 1206
G06F 1300

395477

A controller capable of performing the flexible addressing of memory modules. In one embodiment, involving cache memory, a cache controller maintains, for each slot in cache memory, a read base address and a write base address for the slot and certain characteristics of the SIMM residing in the slot. The use of separate write and read addresses permits more than one cache memory SIMM to be written to with a single write address and permits cache memory to be non-contiguous and thus more robust with respect to SIMM failures. The maintenance of a table of SIMM characteristics permits volatile and non-volatile SIMMs to be used together in cache memory.