Jeremiah F Palmer, 46816 Falkland Trce, Pflugerville, TX 78660

2004020, Oct 14, 2004

Apr 11, 2003

10/412490

Jeremiah Palmer - Pflugerville TX, US
Perry Pelley - Austin TX, US

G11C011/00

365/154000

A memory device () includes a plurality of memory cells (), bit lines, word lines, a sense amplifier (), and a self-timed latch (). The sense amplifier (), responsive to a sense enable signal, is for sensing and amplifying a voltage on the bit lines corresponding to a stored logic state of a selected one of the plurality of memory cells. An isolation circuit () is coupled between the bit lines (and ) and the sense amplifier (). The isolation circuit () is for decoupling the selected one of the plurality of memory cells from the sense amplifier () at about the same time that the sense enable signal is asserted. A self-timed latch () is coupled to the sense amplifier (). The self-timed latch () does not receive a clock signal and is responsive to only the amplified voltage.

2005004, Feb 24, 2005

Aug 22, 2003

10/646081

Jeremiah Palmer - Round Rock TX, US

H03K019/00

326093000

A circuit provides latched data in a domino circuit environment. The circuit receives a pair of input signals that are either in complementary logic states, which is data, or in the same logic state, which is the reset condition. The circuit responds to the complementary logic states by providing intermediate signals and output signals in corresponding complementary logic states. The intermediate logic states are latched by cross-coupled clocked inverters prior to the pair of signals switching from data to reset. The intermediate signals are thus latched in the complementary logic states that correspond to data even after the pair of input signals have returned to reset. The output signals are also thus provided in complementary logic states that correspond to data prior to the input signals being reset.

2006002, Feb 2, 2006

Jul 29, 2004

10/902204

George Hoekstra - Austin TX, US
Jeremiah Palmer - Round Rock TX, US

H03K 19/096

326096000

A circuit () that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit () functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit () latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).

2006026, Nov 23, 2006

May 19, 2005

11/132457

Prashant Kenkare - Austin TX, US
Jeremiah Palmer - Round Rock TX, US

G11C 8/00

365230050

Storage circuits (-and -) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit ), shared complementary write bit lines (), separate read bit lines (-), a shared read word line (), and separate write word lines (-) are used. In an alternate embodiment (e.g. circuit ), shared complementary write bit lines (), a shared read bit line (), separate read word lines (-), and separate write word lines (-) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (), a branch unit (), an SRAM (), other modules (), a cache (), a buffer (), and/or a memory ().

2008002, Jan 24, 2008

Oct 1, 2007

11/865495

Prashant Kenkare - Austin TX, US
Jeremiah Palmer - Round Rock TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 12/00

711128000, 711E12001

Storage circuits (-and -) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit ), shared complementary write bit lines (), separate read bit lines (-), a shared read word line (), and separate write word lines (-) are used. In an alternate embodiment (e.g. circuit ), shared complementary write bit lines (), a shared read bit line (), separate read word lines (-), and separate write word lines (-) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (), a branch unit (), an SRAM (), other modules (), a cache (), a buffer (), and/or a memory ().

2020004, Feb 13, 2020

Jan 17, 2018

16/478611

- Houston TX, US
Jeremiah PALMER - Houston TX, US
Ali SHAJII - Houston TX, US
Daniel MASSE - Houston TX, US
Walter KLEMP - Houston TX, US
David ROBERTSON - Houston TX, US
Robert CROWLEY - Houston TX, US

A61B 17/225
G10K 11/28
G10K 15/04

Apparatuses and methods for generating therapeutic compressed acoustic waves (e.g., shock waves) with an improved acoustic wavefront. In the apparatuses, a housing is defined by a chamber and a shockwave outlet, the chamber is configured to be filed with liquid, a plurality of electrodes defining one or more spark gaps and an acoustic reflector can disposed in the chamber, and a pulse generation system configured to apply voltage pulses to the electrodes at a rate of between 10 Hz and 5 MHz. The improved acoustic wavefront is achieved via a free-form acoustic reflector and/or a stable spark gap location. The free-form acoustic reflector is designed according to a disclosed method including iterating reflector shape using spline interpolation based on defined variables. Additionally, a stable spark gap location is achieved via a single servomotor that adjusts both electrodes simultaneously.