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Jeremy M Hirst, 478429 Milky Way, Citrus Heights, CA 95662

Known as:
James M Hirst Jeremy Hirst Miles
Related to:
Deborah L Chessher 72

Jeremy Hirst Phones & Addresses

8429 Milky Way, Orangevale, CA 95662   

267 700, Provo, UT 84606   

Folsom, CA   

Rancho Cordova, CA   

Sacramento, CA   

Elk Grove, CA   

Austin, TX   

267 E 700 N APT 2, Provo, UT 84606   

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Career records & work history

Medicine Doctors

Jeremy M. Hirst

Specialties:
Psychiatry
Work:
UCSD Medical GroupUCSD Moores Cancer Center
3855 Health Sciences Dr, La Jolla, CA 92093
858-8226100 (phone) 858-2461847 (fax)
Site
UCSD Thornton Psychiatry
9300 Campus Pt Dr, La Jolla, CA 92037
858-8225381 (phone) 619-5437013 (fax)
Education:
Medical School
University of Rochester School of Medicine and Dentistry
Graduated: 2002
Procedures:
Psychiatric Diagnosis or Evaluation, Psychiatric Therapeutic Procedures
Conditions:
Anxiety Phobic Disorders, Anxiety Dissociative and Somatoform Disorders, Attention Deficit Disorder (ADD), Autism, Bipolar Disorder, Dementia, Depressive Disorders, Eating Disorders, Obsessive-Compulsive Disorder (OCD)
Languages:
English
Description:
Dr. Hirst graduated from the University of Rochester School of Medicine and Dentistry in 2002. He works in La Jolla, CA and 1 other location and specializes in Psychiatry. Dr. Hirst is affiliated with UCSD Medical Center and UCSD Thornton Hospital.
Jeremy Hirst Photo 1

Jeremy Mason Hirst

Specialties:
Psychiatry
Child & Adolescent Psychiatry
Education:
University of Rochester(2002)

Jeremy Hirst resumes & CV records

Resumes

Jeremy Hirst Photo 21

Component Engineer

Location:
Orangevale, CA
Industry:
Semiconductors
Work:
Micron Technology
Component Engineer
Jeremy Hirst Photo 22

Jeremy Hirst

Location:
United States

Publications & IP owners

Us Patents

Write Operation For Phase Change Memory

US Patent:
8320172, Nov 27, 2012
Filed:
Jul 29, 2010
Appl. No.:
12/846775
Inventors:
Hernan A. Castro - Shingle Springs CA, US
Jeremy Hirst - Orangevale CA, US
Stephen Tang - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/50
US Classification:
365163, 365148, 365149, 365204
Abstract:
Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell.

Programming Phase Change Memories Using Ovonic Threshold Switches

US Patent:
8374022, Feb 12, 2013
Filed:
Dec 21, 2009
Appl. No.:
12/642915
Inventors:
Timothy C. Langtry - San Jose CA, US
Richard Dodge - Santa Clara CA, US
Hernan Castro - Shingle Springs CA, US
Derchang Kau - Cupertino CA, US
Stephen Tang - Fremont CA, US
Jeremy Hirst - Orangevale CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/00
US Classification:
365163, 365158
Abstract:
A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.

Apparatuses, Devices And Methods For Sensing A Snapback Event In A Circuit

US Patent:
2013004, Feb 21, 2013
Filed:
Aug 18, 2011
Appl. No.:
13/213018
Inventors:
Jeremy Hirst - Orangevale CA, US
Hernan Castro - Shingle Springs CA, US
Stephen Tang - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
G11C 7/10
G05B 24/02
G11C 7/00
US Classification:
365163, 365191, 36518906, 323318, 365148
Abstract:
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Three-State Programming Of Memory Cells

US Patent:
2022024, Aug 4, 2022
Filed:
Apr 22, 2022
Appl. No.:
17/727493
Inventors:
- Boise ID, US
Jeremy M. Hirst - Orangevale CA, US
Shanky K. Jain - Folsom CA, US
Richard K. Dodge - Santa Clara CA, US
William A. Melton - Shingle Springs CA, US
International Classification:
G11C 13/00
Abstract:
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

Memory Device Architecture

US Patent:
2021028, Sep 9, 2021
Filed:
May 24, 2021
Appl. No.:
17/329028
Inventors:
- Boise ID, US
Everardo Torres Flores - Folsom CA, US
Jeremy M. Hirst - Orangevale CA, US
International Classification:
G11C 13/00
G11C 5/02
G11C 5/06
H01L 27/24
Abstract:
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Stored Charge Use In Cross-Point Memory

US Patent:
2021002, Jan 21, 2021
Filed:
Oct 7, 2020
Appl. No.:
17/065295
Inventors:
- Boise ID, US
Jeremy M. Hirst - Orangevale CA, US
Eric S. Carman - San Francisco CA, US
International Classification:
G11C 13/00
Abstract:
Methods, a memory device, and a system are disclosed to reduce power consumption in a cross-point memory device, including providing a first portion of a first pulse of a memory operation to a memory cell at a first time using a first capacitive discharge from a first discharge path, and providing a second portion of the first pulse of the memory operation to the memory cell at a second time, later than the first time, using a second discharge path.

Operational Signals Generated From Capacitive Stored Charge

US Patent:
2019036, Nov 28, 2019
Filed:
Aug 6, 2019
Appl. No.:
16/533208
Inventors:
- Boise ID, US
Jeremy M. Hirst - Orangevale CA, US
Eric S. Carman - San Francisco CA, US
International Classification:
G11C 13/00
Abstract:
Methods, a memory device, and a system are disclosed. One such method includes providing a first pulse to one of multiple bit lines of a variable resistance memory structure at a first time using a first transistor, a second pulse to the one of the multiple bit lines at a second time later than the first time using the first transistor, and a third pulse to the one of the multiple bit lines at a third time later than the second time using a second transistor.

Pulsed Integrator And Memory Techniques

US Patent:
2019015, May 23, 2019
Filed:
Nov 22, 2017
Appl. No.:
15/821240
Inventors:
- Boise ID, US
Jeremy M. Hirst - Orangevale CA, US
International Classification:
G11C 13/00
Abstract:
Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.

Possible Relatives

Cynthia E Hirst  David M Hirst  Dawn H Hirst  Debra A Hirst  Daniel F Hirst  Aaron M Hirst  Donald R Hirst  Jeremy Johnson  Jeremy D Stamps  Jeremy D Standiford 

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