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Jerrold L Allen, 733586 Helen Dr, Pleasanton, CA 94588

Known as:
Jerrold Living Allen Jerrie L Allen Gerrold L Allen
Related to:
Ursula Leah Hunter 54

Jerrold Allen Phones & Addresses

3586 Helen Dr, Pleasanton, CA 94588   

Poway, CA   

San Diego, CA   

Vallejo, CA   

Alameda, CA   

Work

Company: Trinity realty inc Address: 6779 Mission St, Daly City, CA 94014 Industries: Real Estate Agents and Managers

Education

Degree: Graduate or professional degree
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Mentions for Jerrold L Allen

Jerrold Allen resumes & CV records

Resumes

Jerrold Allen Photo 15

Jerrold Allen

Location:
United States
Jerrold Allen Photo 16

Project Management Professional (Pmp)

Location:
San Francisco, California
Industry:
Information Technology and Services
Skills:
Program Management, PMP, Consulting, SDLC, Project Management, PMO, PMI, Governance, Vendor Management, Requirements Analysis, Business Analysis, ITIL, Process Improvement, IT Strategy, MS Project, Visio

Publications & IP owners

Us Patents

Direct Execution Of Software On Microprogrammable Hardware

US Patent:
4747044, May 24, 1988
Filed:
Aug 23, 1984
Appl. No.:
6/643512
Inventors:
Carson T. Schmidt - Poway CA
Chenyu Chao - San Diego CA
Gregory D. Brinson - Escondido CA
Jerrold L. Allen - San Diego CA
Barry L. Loges - San Diego CA
Timothy G. Goldsbury - Excondito CA
Robert O. Gunderson - Poway CA
Jerry K. Herreweyers - San Diego CA
Assignee:
NCR Corporation - Dayton OH
International Classification:
G06F 1308
US Classification:
364200
Abstract:
A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory. The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.

Data Handling System For Handling Data Transfers Between A Cache Memory And A Main Memory

US Patent:
4646237, Feb 24, 1987
Filed:
Dec 5, 1983
Appl. No.:
6/558249
Inventors:
Jerrold L. Allen - San Diego CA
Assignee:
NCR Corporation - Dayton OH
International Classification:
G06F 1300
G06F 1200
US Classification:
364200
Abstract:
In a data handling system having one or more processors, a cache memory associated with each processor and a main memory unit, each cache memory is divided into an equal number of portions, and the main memory is divided into a corresponding number of portions. A data transfer bus is provided between each group of cache memory portions and the corresponding portion of main memory such that each group of cache memory portions corresponds to only a portion of main memory. Each data transfer bus in independently controlled such that the rate of data transfers for the system as a whole is increased.

Possible Relatives

Cynthia M Allen  David A Allen  Cyril J Allen  Davida N Allen  Davie C Allen  Davone L Allen  Dawn Allen  Jerrold M Johnson  Jerrold Jones  Jerrold S Stapleton 

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