Jerry Che Jen Hu, 59PO Box 655303, Dallas, TX 75265

6352900, Mar 5, 2002

Jul 18, 2000

09/618404

Manoj Mehrotra - Dallas TX
Jerry Che-Jen Hu - Plano TX
Amitava Chatterjee - Plano TX
Mark S. Rodder - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 21336

438305, 438303, 438306, 438514, 438519, 438527

A method for controlled oxide growth on transistor gates. A first film ( ) is formed on a semiconductor substrate ( ). The film is implanted with a first species and patterned to form a transistor gate ( ). The transistor gate ( ) and the semiconductor substrate ( ) is implanted with a second species and the transistor gate ( ) oxidized to produce an oxide film ( ) on the side surface of the transistor gate ( ).

6420236, Jul 16, 2002

Aug 17, 2000

09/641053

Jerry C. Hu - Plano TX
Hong Yang - Dallas TX
Amitava Chatterjee - Plano TX
Ih-Chin Chen - Richardson TX

Texas Instruments Incorporated - Dallas TX

H01L 21336

438291, 438299, 438305, 438627

A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming a gate oxide layer on a semiconductor substrate, forming a dummy gate on the substrate, removing the dummy gate after further processing and depositing a lower metallic gate material on said gate oxide; treating the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing an upper gate metal over the lower gate material.

6563175, May 13, 2003

Sep 24, 2001

09/961615

Wei-Tsun Shiau - Plano TX
Craig T. Salling - Plano TX
Jerry Che-Jen Hu - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2362

257355, 257347, 257344, 257384, 257401

An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

6835623, Dec 28, 2004

Feb 24, 2003

10/374333

Wei-Tsun Shiau - Plano TX
Craig T. Salling - Plano TX
Jerry Che-Jen Hu - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 218232

438286, 438682, 438683, 438279

An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

2001003, Nov 8, 2001

Jan 14, 1999

09/231500

JERRY CHE-JEN HU - PLANO TX, US
STEVE HSIA - SAN JOSE CA, US
IH-CHIN CHEN - RICHARDSON TX, US

H01L029/76
H01L021/336

257/384000, 438/300000

A method for forming a ultra-shallow junction region (). A silicon film (single crystalline, polycrystalline or amorphous) is deposited on the substrate () to form an elevated S/D (). A metal film is deposited over the silicon film and reacted with the silicon film to form a silicide film (). The silicon film is preferably completely consumed by the silicide film formation. An implant is performed to implant the desired dopant either into the metal film prior to silicide formation or into the silicide film after silicide formation. A high temperature anneal is used to drive the dopant out of the silicide film to form the junction regions () having a depth in the substrate () less than 200 . This high temperature anneal may be one of the anneals that are part of the silicide process or it may be an additional process step.

2003008, May 1, 2003

Oct 31, 2001

10/001338

Jerry Hu - Plano TX, US
Kwame Eason - Palo Alto CA, US
Rajesh Khamankar - Irving TX, US
Mark Rodder - Universlty Park TX, US
Paul Nicollian - Dallas TX, US
Sunil Hattangady - McKinney TX, US

H01L031/0328
H01L029/94
H01L021/31

257/410000, 438/775000, 438/776000, 257/411000

A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.

2003015, Aug 21, 2003

Mar 13, 2003

10/388946

Jerry Hu - Plano TX, US
Paul Nicollian - Dallas TX, US
Kwame Eason - Palo Alto CA, US
Rajesh Khamankar - Irving TX, US
Mark Rodder - University Park TX, US
Sunil Hattangady - McKinney TX, US

H01L021/336
H01L021/31

438/287000, 438/769000, 438/770000, 438/776000

A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.

2009015, Jun 18, 2009

Dec 18, 2007

11/959111

Haowen Bu - Plano TX, US
Jerry Che-Jen Hu - Plano TX, US
Rajesh Khamankar - Coppell TX, US

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

H01L 29/94
H01L 21/31
H01L 21/8238
H01L 23/58

257369, 257637, 438792, 438199, 257E2124, 257E21632, 257E23001, 257E29345

Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.