Ji Y Kim, 65Los Angeles, CA

7084070, Aug 1, 2006

Jul 17, 2003

10/623016

Sangheon Lee - San Jose CA, US
Sean S. Kang - Fremont CA, US
S M Reza Sadjadi - Saratoga CA, US
Subhash Deshmukh - Vancouver WA, US
Ji Soo Kim - Pleasanton CA, US

Lam Research Corporation - Fremont CA

H01L 21/461
H01L 21/302

438714, 738723, 738724, 738725, 134 11, 134 12, 134 13

A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CHCOOH) or acetic acid/ammonium hydroxide (NHOH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a Hplasma. BTA passivation may be optionally performed on the substrate.

7098130, Aug 29, 2006

Dec 16, 2004

11/016304

Ji Soo Kim - Pleasanton CA, US
Sangheon Lee - Sunnyvale CA, US
S. M. Reza Sadjadi - Saratoga CA, US

LAM Research Corporation - Fremont CA

H01L 21/4763

438638, 438633

A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.

7390749, Jun 24, 2008

Nov 9, 2006

11/558238

Ji Soo Kim - Pleasanton CA, US
Sangheon Lee - Sunnyvale CA, US
Daehan Choi - Milpitas CA, US
S. M. Reza Sadjadi - Saratoga CA, US

Lam Research Corporation - Fremont CA

H01L 21/311

438702, 438241, 438275, 438587, 438737, 257E21691, 257E21683, 257E2166, 257E21678

A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed.

7455748, Nov 25, 2008

Jun 20, 2003

10/600191

Douglas L. Keil - Fremont CA, US
Lumin Li - Santa Clara CA, US
Eric A. Hudson - Berkeley CA, US
Reza Sadjadi - Saratoga CA, US
Eric H. Lenz - Pleasanton CA, US
Rajinder Dhindsa - San Jose CA, US
Ji Soo Kim - Pleasanton CA, US

Lam Research Corporation - Fremont CA

C23F 1/00
H01L 21/306
C23C 16/00

15634546, 118723 E

A plasma processing apparatus for processing a substrate is provided. A plasma processing chamber with chamber walls is provided. A substrate support is provided within the chamber walls. At least one confinement ring is provided, where the confinement ring and the substrate support define a plasma volume. A magnetic source for generating a magnetic field for magnetically enhancing physical confinement provided by the at least one confinement ring is provided.

7476610, Jan 13, 2009

Nov 10, 2006

11/598242

Ji Soo Kim - Pleasanton CA, US
Conan Chiang - Los Altos CA, US
Daehan Choi - Sunnyvale CA, US
S. M. Reza Sadjadi - Saratoga CA, US
Michael Goss - Mendon MA, US

Lam Research Corporation - Fremont CA

H01L 21/44

438628, 438637, 438639, 438695, 438710, 438759, 257E21038, 257E21039, 257E21252, 257E21507, 257E21549

A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

7491647, Feb 17, 2009

Sep 9, 2005

11/223363

S. M. Reza Sadjadi - Saratoga CA, US
Peter Cirigliano - Sunnyvale CA, US
Ji Soo Kim - Pleasanton CA, US
Zhisong Huang - Fremont CA, US
Eric A. Hudson - Berkeley CA, US

Lam Research Corporation - Fremont CA

H01L 21/311

438696, 438637, 438942, 438949, 257E21023

A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

7772122, Aug 10, 2010

Sep 18, 2008

12/233517

Peter Cirigliano - Sunnyvale CA, US
Helen Zhu - Fremont CA, US
Ji Soo Kim - Pleasanton CA, US
S. M. Reza Sadjadi - Saratoga CA, US

Lam Research Corporation - Fremont CA

H01L 21/311

438696, 438699, 438702, 430313

An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.

7838086, Nov 23, 2010

Oct 16, 2008

12/252887

Douglas L. Keil - Fremont CA, US
Lumin Li - Santa Clara CA, US
Eric A. Hudson - Berkeley CA, US
Reza Sadjadi - Saratoga CA, US
Eric H. Lenz - Pleasanton CA, US
Rajinder Dhindsa - San Jose CA, US
Ji Soo Kim - Pleasanton CA, US

Lam Research Corporation - Fremont CA

H05H 1/02
C23C 16/00

427571, 427569, 118723 E

A method for processing a substrate is provided. The substrate is placed in a process chamber. A gas is provided from a gas source to the process chamber. A plasma is generated from the gas in the process chamber. The gas flows through a gap adjacent to at least one confinement ring to provide physical confinement of the plasma. Magnetic confinement of the plasma is provided to enhance the physical confinement of the plasma.