Jianwei Liu, 615504 Esquel Cv, Austin, TX 78739

6954773, Oct 11, 2005

Sep 28, 2001

09/966022

Jianwei Liu - Austin TX, US

Intel Corporation - Santa Clara CA

G06F007/50

708710

In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit adders.

6986023, Jan 10, 2006

Aug 9, 2002

10/215756

Nigel C. Paver - Austin TX, US
William T. Maghielse - Austin TX, US
Wing K. Yu - Chandler AZ, US
Jianwei Liu - Austin TX, US
Anthony Jebson - Austin TX, US
Kailesh B. Bavaria - Austin TX, US
Rupal M. Parikh - Austin TX, US
Deli Deng - Austin TX, US
Mukesh Patel - Austin TX, US
Mark Fullerton - Austin TX, US
Murli Ganeshan - Austin TX, US
Stephen J. Strazdus - Chandler AZ, US

Intel Corporation - Santa Clara CA

G06F 15/16

712 34, 712221, 712223, 712234, 708525

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

7328230, Feb 5, 2008

Mar 26, 2004

10/814990

Bradley C. Aldrich - Austin TX, US
Nigel C. Paver - Austin TX, US
Jianwei Liu - Austin TX, US

Intel Corporation - Santa Clara CA

G06F 7/38

708445

According to some embodiments, a Single-Instruction/Multiple-Data averaging operation is presented. The averaging operation averages multiple sets of data elements, for example, two data elements each from a first source and a second source, producing a set of averages. In at least one embodiment, in a first adder stage, a first plurality of data elements are added to a second plurality of data elements, generating a plurality of intermediate results. In a second adder stage, multiple different combinations of the plurality of intermediate results are added together, generating a plurality of sum results. The two least significant bits of each sum result are discarded.

7529423, May 5, 2009

Mar 26, 2004

10/814991

Bradley C. Aldrich - Austin TX, US
Nigel C. Paver - Austin TX, US
Jianwei Liu - Austin TX, US

Intel Corporation - Santa Clara CA

G06K 9/38

382272, 382260, 382282, 358 327, 358538, 358452

According to some embodiments, a Single-Instruction/Multiple-Data (SIMD) averaging instruction is used to process pixels of image data. The averaging instruction generates a set of four-pixel averages, where each average is generated from two pixels in a first source register and two pixels in a second source register. The first source register contains a plurality of pixels from a first row of pixels and the second source register contains a plurality of pixels from a second row. In one embodiment, the first and second rows are adjacent rows in an image and the averaging instruction is used, for example, to down-scale an image, perform color conversion, and the like. In another embodiment, the first and second rows are from different images and the averaging instruction is used, for example, in motion estimation for video encoding, in motion compensation for video decoding, and the like.