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Jianyu Y Zhu, 46La Jolla, CA

Jianyu Zhu Phones & Addresses

La Jolla, CA   

11874 Ramsdell Ct, San Diego, CA 92131   

12940 Claymont Ct, San Diego, CA 92130   

10361 Azuaga St, San Diego, CA 92129   

10361 Azuaga St #189, San Diego, CA 92129   

8655 Andromeda Rd, San Diego, CA 92126    520-8877878   

Peoria, AZ   

Escondido, CA   

Tucson, AZ   

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Jianyu Y Zhu
Jianyu Y Zhu

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Work

Company: Maxlinear Sep 2009 Position: Rf/mixed-signal ic design engineer

Education

Degree: MS School / High School: University of Arizona 2000 to 2002 Specialities: Electrical Engineering

Industries

Semiconductors

Mentions for Jianyu Y Zhu

Jianyu Zhu resumes & CV records

Resumes

Jianyu Zhu Photo 16

Rf/Mixed-Signal Ic Design Engineer At Maxlinear

Position:
RF/Mixed-Signal IC Design Engineer at MaxLinear
Location:
Greater San Diego Area
Industry:
Semiconductors
Work:
MaxLinear since Sep 2009
RF/Mixed-Signal IC Design Engineer
UCSD Aug 2005 - Aug 2009
Research Assistant
MaxLinear Apr 2008 - Sep 2008
RF/Mixed-Signal IC Design Intern
Hewlett-Packard May 2002 - Jul 2005
Hardware Design Engineer
Education:
University of Arizona 2000 - 2002
MS, Electrical Engineering
Tsinghua University 1996 - 2000
BS, Electrical Engineering

Publications & IP owners

Us Patents

Multi-Layer Time-Interleaved Analog-To-Digital Convertor (Adc)

US Patent:
2012030, Dec 6, 2012
Filed:
May 31, 2012
Appl. No.:
13/485003
Inventors:
Jianyu Zhu - San Diego CA, US
Sheng-Yu Peng - Taiwan, CN
Rodney Chandler - San Diego CA, US
Pawan Tiwari - Irvine CA, US
Rahul Bhatia - San Marcos CA, US
Eric Fogleman - San Marcos CA, US
International Classification:
H03M 1/12
H04B 1/16
US Classification:
455341, 455130, 341122
Abstract:
A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

Digital-To-Analog Converter (Dac) With Partial Constant Switching

US Patent:
2019011, Apr 18, 2019
Filed:
Dec 12, 2018
Appl. No.:
16/217348
Inventors:
- Carlsbad CA, US
Tao Zeng - Carlsbad CA, US
Shantha Murthy Prem Swaroop - Carlsbad CA, US
Jianyu Zhu - Carlsbad CA, US
International Classification:
H03M 1/06
Abstract:
A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Digital-To-Analog Converter (Dac) With Partial Constant Switching

US Patent:
2018028, Oct 4, 2018
Filed:
Jun 4, 2018
Appl. No.:
15/997336
Inventors:
- Carlsbad CA, US
Tao Zeng - Carlsbad CA, US
Shantha Murthy Prem Swaroop - Carlsbad CA, US
Jianyu Zhu - Carlsbad CA, US
International Classification:
H03M 1/06
H03M 1/66
Abstract:
A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Dynamic Power Switching In Current-Steering Dacs

US Patent:
2018024, Aug 30, 2018
Filed:
Apr 30, 2018
Appl. No.:
15/966066
Inventors:
- Carlsbad CA, US
Jianyu Zhu - San Diego CA, US
International Classification:
H03M 1/08
H04B 15/02
H03M 1/66
H03M 1/00
H03M 1/74
Abstract:
Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Localized Dynamic Element Matching And Dynamic Noise Scaling In Digital-To-Analog Converters (Dacs)

US Patent:
2018009, Mar 29, 2018
Filed:
Aug 21, 2017
Appl. No.:
15/681857
Inventors:
- Carlsbad CA, US
Jianyu Zhu - San Diego CA, US
International Classification:
H03M 1/08
H03M 1/66
H03M 1/06
H03M 1/74
Abstract:
Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC.

Digital-To-Analog Converter (Dac) With Partial Constant Switching

US Patent:
2018006, Mar 1, 2018
Filed:
Oct 23, 2017
Appl. No.:
15/790343
Inventors:
- Carlsbad CA, US
Tao Zeng - Carlsbad CA, US
Shantha Murthy Prem Swaroop - Carlsbad CA, US
Jianyu Zhu - Carlsbad CA, US
International Classification:
H03M 1/06
H03M 1/66
Abstract:
Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.

Digital-To-Analog Converter (Dac) With Digital Offsets

US Patent:
2017035, Dec 14, 2017
Filed:
Jun 26, 2017
Appl. No.:
15/633157
Inventors:
- Carlsbad CA, US
Tao Zeng - Carlsbad CA, US
Shantha Murthy Prem Swaroop - Carlsbad CA, US
Jianyu Zhu - Carlsbad CA, US
International Classification:
H03M 1/10
H03M 1/06
H03M 1/68
Abstract:
Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Dynamic Power Switching In Current-Steering Dacs

US Patent:
2017027, Sep 21, 2017
Filed:
Jun 2, 2017
Appl. No.:
15/611827
Inventors:
- Carlsbad CA, US
Jianyu Zhu - San Diego CA, US
International Classification:
H03M 1/08
H03M 1/00
H03M 1/66
H04B 15/02
H03M 1/74
Abstract:
Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

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