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Jihwan P Choi, 49San Diego, CA

Known as:
Ji Hwan Choi
Related to:
Joong J Choi 70

Jihwan Choi Phones & Addresses

San Diego, CA   

Cupertino, CA   

San Jose, CA   

Santa Clara, CA   

Cambridge, MA   

New Providence, NJ   

Mattapan, MA   

70 Pacific St #565, Cambridge, MA 02139   

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Graduate or professional degree
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Jihwan Choi resumes & CV records

Resumes

Jihwan Choi Photo 22

Jihwan Choi

Jihwan Choi Photo 23

Assistant Professor At Dgist

Position:
Assistant Professor at DGIST
Location:
Korea
Industry:
Research
Work:
DGIST - Daegu, Korea since Jan 2013
Assistant Professor Marvell Semiconductor - Santa Clara, CA Sep 2006 - Dec 2012
Systems engineer (Senior, Staff, Senior Staff, and Principal)
Education:
Massachusetts Institute of Technology 1998 - 2006
PhD/MS, EECS Seoul National University 1994 - 1998

Publications & IP owners

Us Patents

Memory Device Etch Methods

US Patent:
7670959, Mar 2, 2010
Filed:
Dec 26, 2006
Appl. No.:
11/616085
Inventors:
Angela T. Hui - Fremont CA, US
Jihwan Choi - San Mateo CA, US
Assignee:
Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438714, 257E21249
Abstract:
A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF) and trifluoromethane (CHF) to etch at least the control gate layer.

Self-Aligned Patterning Method By Using Non-Conformal Film And Etch Back For Flash Memory And Other Semiconductor Applications

US Patent:
7732276, Jun 8, 2010
Filed:
Apr 26, 2007
Appl. No.:
11/796582
Inventors:
Shenqing Fang - Fremont CA, US
Jihwan Choi - San Mateo CA, US
Calvin Gabriel - Cupertino CA, US
Fei Wang - San Jose CA, US
Angela Hui - Fremont CA, US
Alexander Nickel - Santa Clara CA, US
Zubin Patel - San Jose CA, US
Phillip Jones - Fremont CA, US
Mark Chang - Los Altos CA, US
Minh-Van Ngo - Fremont CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/336
US Classification:
438257, 257E293, 257315
Abstract:
A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Systems And Methods For Computing A Relative Path Delay Between Multiple Transmission Sources

US Patent:
7782751, Aug 24, 2010
Filed:
Jul 21, 2008
Appl. No.:
12/176976
Inventors:
Jungwon Lee - Cupertino CA, US
Jiwoong Choi - Santa Clara CA, US
Jihwan P. Choi - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04J 11/00
H04J 3/06
US Classification:
370206, 370252, 370350
Abstract:
Systems and methods are provided for computing a relative path delay between multiple transmitting source to select a source that is closest to a receiving device. Preamble sequences unique to each source are received by a receiving device. The receiving devices determines based on a channel estimation or differential algorithm which transmitting source is closer to the receiving device. The channel estimation algorithm computes the path delay based on a channel estimation correlation at different preamble sequence indices. The differential algorithm computes the path delay based on a correlation between the received and transmitted preamble sequences at different preamble sequence indices. The receiving device selects the closer of the multiple sources to be the source from which to extract data.

Dual Storage Node Memory Devices And Methods For Fabricating The Same

US Patent:
7785965, Aug 31, 2010
Filed:
Sep 8, 2006
Appl. No.:
11/530145
Inventors:
Unsoon Kim - San Jose CA, US
Kyunghoon Min - Palo Alto CA, US
Ning Cheng - San Jose CA, US
Hiroyuki Kinoshita - San Jose CA, US
Timothy Thurgate - Sunnyvale CA, US
Angela Hui - Fremont CA, US
Jihwan Choi - San Mateo CA, US
Chi Chang - Saratoga CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/336
US Classification:
438264, 257E21679
Abstract:
Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

Wordline Resistance Reduction Method And Structure In An Integrated Circuit Memory Device

US Patent:
7867899, Jan 11, 2011
Filed:
Apr 29, 2008
Appl. No.:
12/111886
Inventors:
Shenqing Fang - Fremont CA, US
Jihwan Choi - San Mateo CA, US
Connie Wang - Mountain View CA, US
Eunha Kim - Menlo Park CA, US
Assignee:
Spansion, LLC - Sunnyvale CA
International Classification:
H01L 21/44
H01L 21/02
US Classification:
438655, 438656, 257E21296, 257E21622, 257E21636, 257388
Abstract:
Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.

Hto Offset And Bl Trench Process For Memory Device To Improve Device Performance

US Patent:
7935596, May 3, 2011
Filed:
Dec 22, 2008
Appl. No.:
12/342008
Inventors:
Ning Cheng - San Jose CA, US
Huaqiang Wu - Burlingame CA, US
Hiro Kinoshita - San Jose CA, US
Jihwan Choi - San Mateo CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/336
US Classification:
438257, 438261, 438265, 438287, 257E29309, 257E21423
Abstract:
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Hto Offset Spacers And Dip Off Process To Define Junction

US Patent:
7943983, May 17, 2011
Filed:
Dec 22, 2008
Appl. No.:
12/342011
Inventors:
Huaqiang Wu - Burlingame CA, US
Hiro Kinoshita - San Jose CA, US
Ning Cheng - San Jose CA, US
Arturo Ruiz - San Jose CA, US
Jihwan Choi - San Mateo CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/336
H01L 27/115
US Classification:
257324, 257E21679, 257E27103, 438257
Abstract:
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.

Initial Ranging Power Control Algorithm For Wimax Mobile Stations

US Patent:
7961641, Jun 14, 2011
Filed:
Apr 24, 2008
Appl. No.:
12/109320
Inventors:
Jihwan P. Choi - Santa Clara CA, US
Jiwon S. Han - San Ramon CA, US
Jungwon Lee - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04J 1/16
US Classification:
370252, 370241, 455421, 455425
Abstract:
A device and method for connecting to a WiMAX network can determine an initial signal strength as a function of an uplink propagation path loss between a mobile device and a base station, a noise and interference level value for the base station, a normalized carrier-to-noise value for ranging, and an offset value. If a connection is not established at the initial signal strength, a signal can be retransmitted at a signal strength equal to the initial signal strength plus a step value, where the step value can be determined by designating a fixed number of steps to be used before reaching maximum transmission power.

Possible Relatives

David Choi  Dae J Choi  Deborah H Choi  Daniel Y Choi  Aaron Choi  Danielle J Choi  Derek W Choi 

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