Jin K Cho, 48San Jose, CA

7724567, May 25, 2010

Jul 3, 2008

12/167821

Sang Dhong - San Jose CA, US
Jin Cho - Palo Alto CA, US
John Wuu - Fort Collins CO, US
Gurupada Mandal - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 11/36

365175, 365 4917, 365174, 365179

A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

7871873, Jan 18, 2011

Mar 27, 2009

12/413174

Witold Maszara - Morgan Hill CA, US
Ming-Ren Lin - Cupertino CA, US
Jin Cho - Palo Alto CA, US
Zoran Krivokapic - Santa Clara CA, US

GLOBAL FOUNDRIES Inc. - Grand Cayman

H01L 21/00
H01L 21/84
H01L 21/336

438164, 438294, 257E21159, 257E2141

A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

8053785, Nov 8, 2011

May 19, 2009

12/468612

Jin Cho - Palo Alto CA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 31/0312

257 77, 257 76, 257328, 257329, 257E31024

A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

8455307, Jun 4, 2013

May 19, 2011

13/111741

Jin Cho - Palo Alto CA, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 21/311
H01L 21/335
H01L 23/44
H01L 29/76

438142, 438700, 257288, 257722, 257E27148, 257E2913

FINFET ICs and methods for their fabrication are provided. In accordance with one embodiment a FINFET IC is fabricated by forming in a substrate a region doped with an impurity of a first doping type. The substrate region is etched to form a recess defining a fin having a height and sidewalls and the recess adjacent the fin is filled with an insulator having a thickness less than the height. Spacers are formed on the sidewalls and a portion of the insulator is etched to expose a portion of the sidewalls. The exposed portion of the sidewalls is doped with an impurity of the first doping type, the exposed sidewalls are oxidized, and the sidewall spacers are removed. A gate insulator and gate electrode are formed overlying the fin, and end portions of the fin are doped with an impurity of a second doping type to form source and drain regions.

8461008, Jun 11, 2013

Aug 15, 2011

13/210086

Jin Cho - Palo Alto CA, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 21/336

438296, 438424, 257401

Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

8464130, Jun 11, 2013

Dec 8, 2008

12/330012

Sang Dhong - San Jose CA, US
Jin Cho - Palo Alto CA, US
John Wuu - Fort Collins CO, US
Gurupada Mandal - San Jose CA, US

G06F 11/00

714763, 714752, 714746

An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

2010000, Jan 7, 2010

Jul 3, 2008

12/167823

Sang Dhong - San Jose CA, US
Jin Cho - Palo Alto CA, US
John Wuu - Fort Collins CO, US
Gurupada Mandal - San Jose CA, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G11C 15/00

365 4917, 365 491

A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

2013017, Jul 11, 2013

Jan 6, 2012

13/345388

Lei Yuan - Sunnyvale CA, US
Jin Cho - Palo Alto CA, US
Jongwook Kye - Pleasanton CA, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 29/78
H01L 21/768

257288, 438672, 257E21585, 257E29255

Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.