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Jing Living Chai, 35Austin, TX

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Austin, TX   

Hayward, CA   

Butte Valley, CA   

942 Colusa Ave, Sunnyvale, CA 94085   

Santa Clara, CA   

Lancaster, CA   

Victorville, CA   

Black Point, CA   

San Jose, CA   

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Jing Chai Photo 34

Jing Chai

Jing Chai Photo 35

Jing Chai

Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing

Publications & IP owners

Us Patents

Semiconductor Laser Having Low Stress Passivation Layer

US Patent:
7567601, Jul 28, 2009
Filed:
May 15, 2007
Appl. No.:
11/749047
Inventors:
Tsurugi Sudo - San Jose CA, US
Ashish Verma - San Jose CA, US
Jing Chai - Fremont CA, US
Sumesh Mani K. Thiyagarajan - Fremont CA, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H01S 5/00
US Classification:
372 4301, 372 4501, 372 4601
Abstract:
A laser diode having a composite passivation layer configured to control parasitic capacitance, especially in high speed laser applications, is disclosed. In one embodiment, a ridge waveguide laser is disclosed and includes: a substrate, an active layer disposed on the substrate, a ridge structure disposed on the active layer, and a contact layer disposed on the ridge structure. A composite passivation layer is disposed substantially laterally to the ridge structure. The composite passivation layer includes a silicon nitride bottom layer, a silicon nitride top layer, and a silicon dioxide middle layer interposed between the bottom and top layers. The passivation layers possess differing stress components that, when combined, cancel out the overall mechanical stress of the passivation layer. This enables relatively thick passivation layers to be employed in high speed laser diodes without increasing the risk of layer stress cracking and laser damage.

Cleaving Edge-Emitting Lasers From A Wafer Cell

US Patent:
7858493, Dec 28, 2010
Filed:
Feb 22, 2008
Appl. No.:
12/036157
Inventors:
Weizhong Sun - Fremont CA, US
Tsurugi Sudo - San Jose CA, US
Jing Chai - Fremont CA, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H01L 21/46
US Classification:
438455, 438456, 438457, 438458, 438459, 438460, 438461, 438462, 438463, 438113, 438114, 438120
Abstract:
In one example embodiment, a process for cleaving a wafer cell includes several acts. First a wafer cell is affixed to an adhesive film. Next, the adhesive film is stretched substantially uniformly. Then, the adhesive film is further stretched in a direction that is substantially orthogonal to a predetermined reference direction. Next, the wafer cell is scribed to form a notch that is oriented substantially parallel to the predetermined reference direction. Finally, the wafer cell is cleaved at a location substantially along the notch.

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