Jing L Guo, 361 Deer Run, Rensselaer, NY 12144

2022039, Dec 8, 2022

Jun 7, 2021

17/340300

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Jing Guo - Niskayuna NY, US
Jennifer Church - Albany NY, US
Luciana Meli - Albany NY, US

G03F 7/039
G03F 7/004
G03F 7/20

Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.

2022019, Jun 23, 2022

Dec 23, 2020

17/132980

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Jing Guo - Niskayuna NY, US
Hao Tang - Slingerlands NY, US
Cheng Chi - Jersey City NJ, US

H01L 29/417
H01L 29/40
H01L 29/45
H01L 29/66
H01L 29/786
H01L 29/08

A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.

2023010, Mar 30, 2023

Sep 24, 2021

17/448777

- ARMONK NY, US
WENYU XU - ALBANY NY, US
INDIRA SESHADRI - NISKAYUNA NY, US
JING GUO - NISKAYUNA NY, US
EKMINI ANUJA DE SILVA - SLINGERLANDS NY, US

H01L 29/78
H01L 21/8238
H01L 27/092
H01L 29/66
H01L 29/40

A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.

2021038, Dec 9, 2021

Jun 6, 2020

16/894774

- Armonk NY, US
Jing Guo - Niskayuna NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Abraham Arceo de la Pena - Albany NY, US

H01L 29/417
H01L 29/40
H01L 29/41

Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

2021014, May 20, 2021

Nov 19, 2019

16/688657

- Armonk NY, US
Jing Guo - Niskayuna NY, US
Jennifer Church - Troy NY, US
Dario Goldfarb - Dobbs Ferry NY, US

G03F 7/004
H01L 21/027

A metal brush layer is provided. The metal brush layer includes a polymer backbone including at least one grafting unit, G, attached to the polymer backbone, and a plurality of metal-containing moieties, M, attached to the polymer backbone.

2021008, Mar 18, 2021

Sep 13, 2019

16/570603

- Armonk NY, US
Jing Guo - Niskayuna NY, US
Luciana Meli - Albany NY, US
Nelson Felix - Slingerlands NY, US

H01L 21/033
H01L 21/027

A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

2021002, Jan 21, 2021

Jul 18, 2019

16/515926

- Armonk NY, US
Ruilong Xie - Niskayuna NY, US
Chih-Chao Yang - Glenmont NY, US
Jing Guo - Niskayuna NY, US

H01L 23/522
H01L 21/768

A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening.

2020040, Dec 24, 2020

Jun 24, 2019

16/450112

- Armonk NY, US
Chih-Chao Yang - Glenmont NY, US
Jing Guo - Niskayuna NY, US
Kangguo Cheng - Schenectady NY, US

H01L 21/768
H01L 23/528
H01L 23/522

A method for fabricating a semiconductor device includes forming at least one sacrificial via within at least one self-aligned via hole of a base structure, forming a region having a misalignment relative to the at least one sacrificial via by cut patterning, and forming a cut cavity having a geometry for minimizing effects of the misalignment by protecting at least one self-aligned via due to the misalignment.