Jingbo B Gao, 541194 Huntingdon Dr, San Jose, CA 95129

2009027, Oct 29, 2009

Dec 30, 2008

12/346004

Bing ZHU - Fremont CA, US
Tung-sun Tung - Cupertino CA, US
Jingbo Gao - Saratoga CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

703 14

A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.

2010031, Dec 16, 2010

Jun 11, 2010

12/814355

Arthur Perry Sarkisian - Tillson NY, US
Jingbo Gao - Saratoga CA, US

G06F 17/50

703 13

A system and method for selectively capturing and storing emulation data results from a hardware emulation system, which reduces the data bandwidth requirement and the unnecessary consumption of the DRAM memory capacity by uninteresting data. According to one embodiment, a system comprises a trace array for storing one or more frames of data; a first set of hardware control bits that enables the trace array to selectively capture non-continuous windows of data within a frame of data; a data capture card; and a second set of hardware control bits that enables the data capture card to capture a select frame of data from the one or more frames of data stored on the trace array.

2022041, Dec 29, 2022

Aug 24, 2022

17/894677

- Nanjing, CN
Jingbo Gao - San Jose CA, US

G01R 31/317
G01R 31/3183

A debug system for debugging a logic design includes an adaptor and a debug station connected to the adaptor. The logic design includes a plurality of design modules. The adaptor is configured to receive an emulation output of the logic design. The emulation output includes a design snapshot of the logic design and input signals to the logic design that both are recorded during an emulation process of the logic design. The debug station is configured to generate, based on the emulation output and a netlist of a design module of the logic design, an emulation history of the design module.

2020024, Jul 30, 2020

Jan 24, 2020

16/752167

Jingbo Gao - San Jose CA, US

G06F 11/36
G06F 1/08

An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.