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Jingjing Liu111 Orr Rd, Alameda, CA 94502

Jingjing Liu Phones & Addresses

111 Orr Rd, Alameda, CA 94502   

San Francisco, CA   

Bryan, TX   

College Station, TX   

Pittsburgh, PA   

Mentions for Jingjing Liu

Career records & work history

Lawyers & Attorneys

Jingjing Liu Photo 1

Jingjing Liu - Lawyer

ISLN:
1000640670
Admitted:
2010

Resumes & CV records

Resumes

Jingjing Liu Photo 36

Designer

Location:
1812 Lee Way, Milpitas, CA 95035
Industry:
Semiconductors
Work:
Form4 Architecture, Inc.
Designer
Applied Materials Aug 1, 2011 - Feb 2017
Senior Process Engineer
University of Wisconsin-Madison Aug 2006 - Aug 2011
Research Assistant
University of Pennsylvania 2008 - 2011
Research Assistant
Univeristy of New Orleans Aug 2004 - Aug 2006
Research Assistant
Education:
Academy of Art University 2017 - 2018
Master of Fine Arts, Masters
University of Wisconsin - Madison 2006 - 2011
Doctorates, Doctor of Philosophy, Materials Science, Engineering, Philosophy
University of Wisconsin - Madison 2010
University of Michigan 2005 - 2006
University of New Orleans 2004 - 2006
Master of Science, Masters, Applied Physics, Physics
Southwest Jiaotong University 1998 - 2005
Master of Science, Masters, Bachelors, Bachelor of Science, Materials Science, Engineering
Southwest Jiaotong University 2002
Skills:
Scanning Electron Microscopy, Afm, Microfabrication, Lithography, Tem, Etching, Cvd, Mems, Nanotechnology, Powder X Ray Diffraction, Ald, Semiconductors, Xrd, Jmp, Doe, Pvd, Rtp, P3I, Icp Oes, Rga, Hardware/Chamber Diagnostics, Semiconductor Fabrication and Process Design, Physical Vapor Deposition, Perspective Drawings, Photoshop, Revit, Adobe Illustrator, Indesign, Interior Architecture, Microsoft Office, Spatial Design, Interior Design, Sketchup
Languages:
English
Mandarin
Jingjing Liu Photo 37

Fund Accounting Manager

Location:
San Francisco, CA
Industry:
Real Estate
Work:
Carmel Partners
Fund Accounting Manager
Carmel Partners Sep 2013 - Sep 2015
Fund Accountant
Carmel Partners Jun 2011 - Aug 2013
Property Accountant
Charles Dunn Company Jul 2008 - Jun 2011
Accountant
Education:
Brigham Young University - Hawaii 2004 - 2008
Bachelors, Bachelor of Science, Accounting
Skills:
Property Management, General Ledger, Yardi, Accounts Payable, Accounts Receivable, Mri Software, Quickbooks, Due Diligence, Cash Flow, Asset Management, Real Estate Economics, Disposition, Financial Reporting, Budgets, Financial Analysis, Accounting, Bank Reconciliation, Variance Analysis, Real Estate, Gaap, Real Estate Development, Financial Modeling, Valuation
Jingjing Liu Photo 38

Test Engineer

Location:
1662 Blossom Hill Rd, San Jose, CA 95124
Industry:
Computer Software
Work:
Google
Test Engineer
Tango Me Sep 2012 - Apr 2016
Software Engineer In Test
Stanford University Jun 2011 - Aug 2011
Software Engineer
Motorola Jul 2007 - Nov 2007
Quality Assurance Software Engineer
Education:
San Francisco State University 2010 - 2012
Master of Science, Masters, Computer Science
Beijing University of Posts and Telecommunications 2006 - 2009
Master of Science, Masters, Computer Science
Qingdao University 2002 - 2006
Bachelors, Bachelor of Science, Computer Science, Software Engineering
Skills:
Java, Python, Testing, C++, Linux, Eclipse, Javascript, Software Development, Junit, Netbeans, Programming, Data Mining, Cloud Computing, Objective C, Distributed Systems, Robotium, Android Sdk, Os X, Mac Os X, Uiautomation
Interests:
Ping Pong
Foosball
Jogging
Badminton
Languages:
English
Mandarin
Jingjing Liu Photo 39

Program Manager

Location:
San Francisco, CA
Industry:
Research
Work:
Lawrence Berkeley National Laboratory
Program Manager
Dnv Gl Jul 1, 2012 - May 2016
Technology Specialist and Senior Engineer
Nexant May 2010 - Jul 2012
Project Engineer
Texas A&M University Aug 2006 - May 2010
Research Assistant
Tsinghua University Sep 2004 - Aug 2006
Graduate Student
Arup Jul 2004 - Aug 2004
Intern
Education:
Texas A&M University 2006 - 2010
Master of Science, Masters
Tsinghua University 2004 - 2006
Master of Science, Masters
Tsinghua University 2000 - 2004
Bachelors, Architecture
Skills:
Energy Efficiency, Energy Audits, Energy Conservation, Hvac, Energy Management, Simulations, Engineering, Modeling, Energy, Data Analysis, Retro Commissioning, Demand Response, Renewable Energy, Building Energy Simulation, Building Simulation, Sustainability, Vba, Project Management, Solar Energy, Architectural Design, Simulation, Acoustics, Mechanical Engineering, Project Planning, Retrofit, Demand Management, Vba Programming, Data Quality, Retrofits, Measurements and Verification, Glass Facade, Building Acoustics, Compressed Air Systems, Steam Systems, Pumping Systems, Process Heating Systems
Languages:
English
Mandarin
Certifications:
Professional Engineer License (California)
Us Doe Qualified Airmaster+ Specialist
Us Doe Qualified Steam Tool Specialist
Us Doe Qualified Process Heating Systems Specialist
Ashrae Beap - Building Energy Assessment Professional
Certified Practitioner In Industrial Energy Management Systems (Cp Enms - Industrial)
Superior Energy Performance (Sep) Performance Verifier - Industrial Sector
Lean Six Sigma Green Belt
Exin Epiâ® Certified Data Centre Professional (Cdcp)
Jingjing Liu Photo 40

Software Engineer

Location:
Milpitas, CA
Industry:
Computer Software
Skills:
C, Python, Algorithms, Machine Learning, Matlab, Perl, Latex, R, Data Mining, Programming, Linux, C++, Java, Computer Science, Software Engineering
Jingjing Liu Photo 41

Sales Director, North America

Location:
San Francisco, CA
Work:
Hanshow Technology
Sales Director, North America
Education:
West Valley College 2018 - 2019
Jingjing Liu Photo 42

Senior Engineer

Location:
San Francisco, CA
Work:
Kla
Senior Engineer
Education:
Purdue University
Jingjing Liu Photo 43

Jingjing Liu

Publications & IP owners

Us Patents

High Temperature Tungsten Metallization Process

US Patent:
2013010, May 2, 2013
Filed:
Oct 25, 2012
Appl. No.:
13/660463
Inventors:
JOSHUA COLLINS - Sunnyvale CA, US
Murali K. Narasimhan - San Jose CA, US
Jingjing Liu - Santa Clara CA, US
Kai Wu - Palo Alto CA, US
Avgerinos V. Gelatos - Redwood City CA, US
International Classification:
H01L 21/768
US Classification:
438653
Abstract:
Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700 C. to less than 1,000 C.). Subsequently, the method includes optionally forming a nucleation layer on the tungsten barrier layer, optionally exposing the tungsten barrier layer and/or the nucleation layer to a reducing agent during soak processes, and forming a tungsten bulk layer on or over the tungsten barrier layer and/or the nucleation layer.

Power Delivery For High Power Impulse Magnetron Sputtering (Hipims)

US Patent:
2018010, Apr 19, 2018
Filed:
Aug 30, 2017
Appl. No.:
15/691157
Inventors:
- Santa Clara CA, US
ADOLPH MILLER ALLEN - Oakland CA, US
MICHAEL STOWELL - Loveland CO, US
ZHONG QIANG HUA - Saratoga CA, US
CARL R. JOHNSON - Tracy CA, US
VANESSA FAUNE - San Jose CA, US
JINGJING LIU - Milpitas CA, US
International Classification:
H01J 37/34
C23C 14/34
C23C 14/35
H01B 9/02
Abstract:
A system for the generation and delivery of a pulsed, high voltage signal for a process chamber includes a remotely disposed high voltage supply to generate a high voltage signal, a pulser disposed relatively closer to the process chamber than the high voltage supply, a first shielded cable to deliver the high voltage signal from the remotely disposed high voltage supply to the pulser to be pulsed, and a second shielded cable to deliver a pulsed, high voltage signal from the pulser to the process chamber. A method for generating and delivering a pulsed, high voltage signal to a process chamber includes generating a high voltage signal at a location remote from the process chamber, delivering the high voltage signal to a location relatively closer to the process chamber be pulsed, pulsing the delivered, high voltage signal, and delivering the pulsed, high voltage signal to the process chamber.

Pulse Shape Controller For Sputter Sources

US Patent:
2018004, Feb 15, 2018
Filed:
Nov 11, 2016
Appl. No.:
15/349433
Inventors:
- Santa Clara CA, US
Viachslav BABAYAN - Sunnyvale CA, US
Jingjing LIU - Milpitas CA, US
Zhong Qiang HUA - Saratoga CA, US
International Classification:
C23C 14/34
H01J 37/34
C23C 14/35
H01L 21/683
Abstract:
Embodiments presented herein relate to a pulse control system for a substrate processing system. The pulse control system includes a power source, a system controller, and a pulse shape controller. The pulse shape controller is coupled to the power source and in communication with the system controller. The pulse shape controller includes a first switch assembly and a second switch assembly. The first switch assembly includes a first switch having a first end and a second end. The first switch is configurable between an open state and a closed state. The second switch assembly includes a second switch having a first end and a second end. The first switch is in the closed state and the second switch is in the open state. The first switch in the closed state is configured to allow a pulse supplied by the power source to transfer through the pulse shape controller.

Nanocrystaline Diamond Carbon Film For 3D Nand Hardmask Application

US Patent:
2017006, Mar 2, 2017
Filed:
Nov 10, 2016
Appl. No.:
15/348170
Inventors:
- Santa Clara CA, US
Christopher S. NGAI - Burlingame CA, US
Jingjing LIU - Milpitas CA, US
Jun XUE - San Jose CA, US
Chentsau YING - Cupertino CA, US
Ludovic GODET - Sunnyvale CA, US
International Classification:
H01L 21/033
H01L 27/115
Abstract:
A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Nanocrystaline Diamond Carbon Film For 3D Nand Hardmask Application

US Patent:
2016006, Mar 3, 2016
Filed:
Aug 24, 2015
Appl. No.:
14/833858
Inventors:
- Santa Clara CA, US
Christopher S. NGAI - Burlingame CA, US
Jingjing LIU - Milpitas CA, US
Chentsau YING - Cupertino CA, US
Ludovic GODET - Sunnyvale CA, US
International Classification:
H01L 29/423
H01L 21/311
H01L 29/51
H01L 21/02
H01L 29/49
H01L 27/115
Abstract:
A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Process For Etching Metal Using A Combination Of Plasma And Solid State Sources

US Patent:
2015009, Apr 9, 2015
Filed:
May 29, 2014
Appl. No.:
14/290861
Inventors:
- Santa Clara CA, US
Joseph Johnson - Redwood City CA, US
Jingjing Liu - Sunnyvale CA, US
He Ren - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/3213
H01L 21/268
US Classification:
438720
Abstract:
An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.

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