Jingyun Zhang2318 Excalibur Dr, Fort Mill, SC 29707

2021024, Aug 12, 2021

Feb 7, 2020

16/784365

- Armonk NY, US
Takashi Ando - Eastchester NY, US
Alexander Reznicek - Troy NY, US
Jingyun Zhang - Albany NY, US

H01L 21/8238
H01L 27/092

Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

2021007, Mar 11, 2021

Sep 5, 2019

16/562388

- Armonk NY, US
Takashi Ando - Eastchester NY, US
Pouya Hashemi - Purchase NY, US
Choonghyun Lee - Rensselaer NY, US
Jingyun Zhang - Albany NY, US

H01L 27/24
H01L 29/78
H01L 45/00
H01L 29/04
H01L 29/10
H01L 29/66
H01L 29/08

A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

2020040, Dec 24, 2020

Jun 20, 2019

16/447614

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Jingyun Zhang - Albany NY, US
Pouya Hashemi - Purchase NY, US
Alexander Reznicek - Troy NY, US

H01L 29/10
H01L 29/78
H01L 29/423
H01L 29/66
H01L 27/092
H01L 21/8238

An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

2020037, Nov 26, 2020

May 22, 2019

16/420118

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Alexander Reznicek - Troy NY, US
Jingyun Zhang - Albany NY, US
Pouya Hashemi - Purchase NY, US

H01L 29/78
H01L 29/161
H01L 29/66
H01L 29/10
H01L 21/02
H01L 21/324
H01L 27/12
H01L 21/84

A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.

2020031, Oct 1, 2020

Mar 26, 2019

16/364651

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Jingyun Zhang - Albany NY, US
Alexander Reznicek - Troy NY, US
Pouya Hashemi - Purchase NY, US

H01L 21/8234
H01L 21/8238
H01L 27/088
H01L 29/10
H01L 29/78

A method for fabricating a semiconductor device including vertical transistors having uniform channel length includes defining a channel length of at least one first fin formed on a substrate in a first device region and a channel length of at least one second fin formed on the substrate in a second device region. Defining the channel lengths includes creating at least one divot in the second device region. The method further includes modifying the channel length of the at least one second fin to be substantially similar to the channel length of the at least one first fin by filling the at least one divot with additional gate conductor material.

2020029, Sep 17, 2020

Mar 15, 2019

16/355148

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Alexander Reznicek - Troy NY, US
Jingyun Zhang - Albany NY, US
Choonghyun Lee - Rensselaer NY, US

H01L 43/12
H01L 27/22

A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

2020025, Aug 13, 2020

Feb 8, 2019

16/271501

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Alexander Reznicek - Troy NY, US
Jingyun Zhang - Albany NY, US
Pouya Hashemi - White Plains NY, US

H01L 27/24
H01L 45/00
H01L 29/78
H01L 29/66

A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.

2020025, Aug 6, 2020

Feb 6, 2019

16/269220

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Alexander Reznicek - Troy NY, US
Jingyun Zhang - Albany NY, US
Choonghyun Lee - Rensselaer NY, US

H01L 29/10
H01L 29/78
H01L 27/092
H01L 29/423
H01L 29/66

Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.