Joaquin Lobo Madruga, 668409 Delavan Ave, Austin, TX 78717

8056080, Nov 8, 2011

Aug 31, 2009

12/551515

Benjamin G. Alexander - Austin TX, US
Gregory H. Bellows - Austin TX, US
Joaquin Madruga - Austin TX, US
Brian D. Watt - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46
G06F 15/00
G06T 15/00

718102, 718103, 718104, 345522, 712 28, 712200, 712215, 712220

Execution units process commands from one or more command queues. Once a command is available on the queue, each unit participating in the execution of the command atomically decrements the command's work groups remaining counter by the work group reservation size and processes a corresponding number of work groups within a work group range. Once all work groups within a range are processed, an execution unit increments a work group processed counter. The unit that increments the work group processed counter to the value stored in a work groups to be executed counter signals completion of the command. Each execution unit that access a command also marks a work group seen counter. Once the work groups processed counter equals the work groups to be executed counter and the work group seen counter equals the number of execution units, the command may be removed or overwritten on the command queue.

8250404, Aug 21, 2012

Dec 31, 2009

12/651188

Benjamin G. Alexander - Austin TX, US
Gregory H. Bellows - Austin TX, US
Joaquin Madruga - Austin TX, US
Barry L. Minor - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 11/00
G06F 11/14

714 13, 714 10, 714 15, 714 381

Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more embodiments, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more embodiments, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing.

8266337, Sep 11, 2012

Dec 6, 2007

11/951435

Joaquin Madruga - Round Rock TX, US
Dean J. Burdick - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 13/28

710 22, 710 23, 710 24, 710 26, 710 27, 710 28

A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

8316207, Nov 20, 2012

Dec 30, 2009

12/649542

Greg H. Bellows - Austin TX, US
Jason N. Dale - Austin TX, US
Brian H. Horton - Pflugerville TX, US
Joaquin Madruga - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 12/02

711202, 711E12014

A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.

8316219, Nov 20, 2012

Aug 31, 2009

12/551526

Gregory H. Bellows - Austin TX, US
Joaquin Madruga - Austin TX, US
Ross A. Mikosh - Austin TX, US
Brian D. Watt - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

712220

Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue.

8401309, Mar 19, 2013

Dec 30, 2008

12/346382

Joaquin Madruga - Round Rock TX, US
Barry L. Minor - Austin TX, US
Michael A. Paolini - Austin TX, US

International Business Machines Corporation - Armonk NY

G06K 9/00

382209, 382218, 711216, 707698, 37039532, 713176, 713180, 725 19, 348161

A mechanism is provided for security screening image analysis simplification through object pattern identification. Popular consumer electronics and other items are scanned in a control system, which creates an electronic signature for each known object. The system may reduce the signature to a hash value and place each signature for each known object in a “known good” storage set. For example, popular mobile phones, laptop computers, digital cameras, and the like may be scanned for the known good signature database. At the time of scan, such as at an airport, objects in a bag may be rotated to a common axis alignment and transformed to the same signature or hash value to match against the known good signature database. If an item matches, the scanning system marks it as a known safe object.

8478968, Jul 2, 2013

May 8, 2012

13/466620

Gregory H. Bellows - Austin TX, US
Joaquin Madruga - Austin TX, US
Ross A. Mikosh - Austin TX, US
Brian D. Watt - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 9/30
G06F 9/40
G06F 15/00

712216

Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue.

8495604, Jul 23, 2013

Dec 30, 2009

12/649652

Gregory H. Bellows - Austin TX, US
Brian H. Horton - Plfugerville TX, US
Joaquin Madruga - Round Rock TX, US
Barry L. Minor - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/45
G06F 15/00

717149, 712 10

A system provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The system comprises: a compiler generating one or more commands from received program instructions; ND Range work processing (WP) logic determining when a command generated by the compiler will be implemented over an ND configuration of operands, where N is greater than one (1); automatically decomposing the ND configuration of operands into a one (1) dimension (1D) work element comprising P sequentially ordered work items that each represent one of the operands; placing the 1D work element within a command queue of the DPS; enabling sequential dispatching of 1D work items in ordered sequence from to one or more processing units; and generating an ND Range output by mapping the 1D work output result to an ND position corresponding to an original location of the operand represented by the 1D work item.