Joe Douglas Bolding, 76Aledo, TX

6826675, Nov 30, 2004

Oct 9, 2001

09/973156

Dan Tormey - Richardson TX
Joe Bolding - Allen TX
Gerald Everett - Alta CA

Hewlett-Packard Development Company, L.P. - Houston TX

G08F 930

712202

A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointers farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

6832181, Dec 14, 2004

Nov 3, 2000

09/706095

Joe D. Bolding - Allen TX
Daniel G. Tormey - Richardson TX

Hewlett-Packard Development Company, L.P. - Houston TX

G06G 762

703 13, 703 21, 703 22

Simulated computer hardware is differentiated from physical computer hardware for user code by detecting a sequence of instructions which produce no effect on physical computer hardware but which set a flag on simulated computer hardware. User code may thus issue the sequence of instructions, then check the flag to determine whether it is executing on simulated hardware or physical hardware.

6859892, Feb 22, 2005

Apr 25, 2001

09/843265

Joe Bolding - Allen TX, US
Dan Tormey - Richardson TX, US
Gerald Everett - Alta CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F011/00

714 34, 714 11

A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.

6862694, Mar 1, 2005

Oct 5, 2001

09/972094

Dan Tormey - Richardson TX, US
Joe Bolding - Allen TX, US
Bjorn Helgaas - Windsor CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F011/00

714 34, 714 35, 714 38, 717129

A system and method for setting and executing breakpoints utilized for debugging program code. A user interface (UI) stores breakpoint addresses in a breakpoint table within a central processing unit (CPU). Multiple breakpoint addresses may be stored in the table as a range of addresses in a single entry. A flag indicates whether each stored address or address range is a physical or virtual address. When executing the program code on the CPU, an instruction core requests from an instruction cache, an instruction associated with a particular address. The cache first determines from the breakpoint table within the CPU whether there is a breakpoint associated with the particular address. If so, the cache returns control to the UI. Otherwise, the cache goes out to a coherency controller to fetch the instruction from memory.

6904513, Jun 7, 2005

Jul 2, 2004

10/884666

Dan Tormey - Richardson TX, US
Joe Bolding - Allen TX, US
Gerald Everett - Alta CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F015/00

712202

A system and method for managing utilization in a stack. A stack base and a stack pointer are initialized for the stack. Upon fetching a program instruction to be executed in a computing environment, a determination is made if the program instruction involves accessing a location within a valid stack range that is defined by a high water mark operable to identify the stack pointer's farthest location from the stack base. The farthest location is indicative of how far the stack has grown at any time during the program's execution. A warning may be provided upon determining that the location to be accessed is not within the valid stack range.

7162743, Jan 9, 2007

Oct 4, 2001

09/971327

Joe Bolding - Allen TX, US
Dan Tormey - Richardson TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 7/04
H04L 9/32

726 27, 726 30, 726 34

A system and method for protecting a defined range of hardware addresses or a defined set of processor instructions from being accessed or executed by unauthorized software modules. Abstraction layer code is given a range of software addresses that are permitted to access the protected addresses or execute the instructions. Authorized accesses must utilize service routines provided by the abstraction layer code. When an attempted access to a protected hardware address is detected, it is determined whether the access is from the abstraction layer code. If so, the access is permitted. If not, the access is prohibited, and an error message is generated. A basic set of authorized processor instructions and an extended set of processor instructions may be defined for a reference platform. Execution of processor instructions in the extended set is limited to authorized abstraction layers. Otherwise, the attempted execution is prohibited, and an error message is generated.

7343590, Mar 11, 2008

Jun 25, 2002

10/178992

Daniel Tormey - Richardson TX, US
Joe Bolding - Allen TX, US
Matt Jacunski - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 9/44

717131, 717135, 718100, 718107, 718108, 719328

A system and method for increasing Operating System (OS) idle loop performance in a simulator environment. Upon encountering an OS idle loop condition on a processor, OS program flow is skipped ahead by an amount of time, thereby conserving the host machine's resources that would otherwise have been spent in supporting the OS idle loop execution. If another processor initiates an inter-processor message directed to a processor whose OS program flow has been skipped forward, that processor is capable of skipping backward in time, if necessary, to service the inter-processor message.

7428695, Sep 23, 2008

Oct 22, 2001

09/986221

Alexander Chiang - Urbana IL, US
Joe D. Bolding - Allen TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06N 3/00

715201

A system that indexes text according to an arbitrary set of indices and automatically generates hyperlinks from each index to a related subject in a document. A text file containing the documentation of interest is used as input to a hyperlink processing program that generates a file containing links to all of the topics of interest. A category file is then created that indicates an association between each of the topics and corresponding subjects included in each topic. Next, a data structure is generated that associates each topic with corresponding subject names. A plurality of subject name files is generated, each including HTML (hypertext markup language) text corresponding to an associated subject, and a file comprising said hyperlinks to each of the subject name files is generated. A plurality of index files is generated, each including hyperlinks between each of the topics and corresponding subject name files. A list of category names corresponding to a primary set of indices is displayed in a first window, and a secondary set of said indices comprising a list of subject names is displayed in a second window, in response to a user selecting one of the category names.