Joel D Peterson, 452713 W Hill Rd, Boise, ID 83702

2022036, Nov 17, 2022

Jul 20, 2022

17/869732

- Boise ID, US
Prakash Rau Mokhna Rau - Boise ID, US
Arun Kumar Dhayalan - Boise ID, US
Damir Fazil - Boise ID, US
Joel D. Peterson - Boise ID, US
Anilkumar Chandolu - Boise ID, US
George Matamis - Eagle ID, US
Christopher Larsen - Boise ID, US
Rokibul Islam - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L 27/11582
G11C 5/02
H01L 21/768
G11C 16/04
G11C 5/06

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

2023006, Mar 2, 2023

Dec 29, 2021

17/564633

- Boise ID, US
Matthew J. King - Boise ID, US
Jason Reece - Boise ID, US
Michael J. Gossman - Meridian ID, US
Shruthi Kumara Vadivel - Boise ID, US
Martin J. Barclay - Middleton ID, US
Lifang Xu - Boise ID, US
Joel D. Peterson - Boise ID, US
Matthew Park - Boise ID, US
Adam L. Olson - Boise ID, US
David A. Kewley - Boise ID, US
Xiaosong Zhang - Boise ID, US
Justin B. Dorhout - Boise ID, US
Zhen Feng Yow - Singapore, SG
Kah Sing Chooi - Singapore, SG
Tien Minh Quan Tran - Singapore, SG
Biow Hiem Ong - Singapore, SG

H01L 23/528
H01L 23/522
H01L 21/768

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

2020012, Apr 23, 2020

Dec 21, 2018

16/230382

- Boise ID, US
Erik Byers - Boise ID, US
Merri L. Carlson - Boise ID, US
Indra V. Chary - Boise ID, US
Damir Fazil - Boise ID, US
John D. Hopkins - Meridian ID, US
Nancy M. Lomeli - Boise ID, US
Eldon Nelson - Dripping Springs TX, US
Joel D. Peterson - Boise ID, US
Dimitrios Pavlopoulos - Glendale CA, US
Paolo Tessariol - Arcore, IT
Lifang Xu - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 27/11582
H01L 27/1157
H01L 21/768
H01L 29/66
H01L 29/792

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material. Elevationally-extending strings of memory cells are formed in the stack. Structure independent of method is disclosed.