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John E Barwin, 6112 Bobolink Cir, Essex Junction, VT 05452

Known as:
John P Barwin
Related to:
Michael L Pressey 85 Michael Scott Pressey 61

John Barwin Phones & Addresses

12 Bobolink Cir, Essex, VT 05452    802-8797396   

Essex Junction, VT   

681 Kinsley Rd, Jeffersonville, VT 05464    802-6442269   

Jeffersonvlle, VT   

East Fairfield, VT   

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John E Barwin

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Work

Company: Globalfoundries Apr 2017 Position: Pmts - product development engineer

Education

Degree: Master of Science, Masters School / High School: University of Vermont 1998 to 2000 Specialities: Engineering

Skills

Asic • Eda • Simulations • Cmos • Vlsi • Physical Design • Circuit Design • Static Timing Analysis • Semiconductors • Spice • Hardware Architecture • Cadence Virtuoso • Functional Verification • Ic • Tcl • Rtl Design • Mixed Signal • Soc • Processors • Analog Circuit Design • Electrical Engineering • Testing • Analog • Embedded Systems • System Architecture • Lvs • Perl • Vhdl • Logic Design • Integrated Circuit Design • Fpga • Verilog • Ddr • Linux • Microprocessors • Timing Closure • Computer Architecture • Firmware • Pcb Design • Algorithms • Team Leadership • Process Improvement • Cadence • Perl Script • Dft • Leading Change • Verilog Ams • Unix • Microelectronics • Synopsis

Industries

Information Technology And Services
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Memory Manage

Location:
1735 Technology Dr, San Jose, CA 95110
Industry:
Information Technology And Services
Work:
Globalfoundries
Pmts - Product Development Engineer Nanya Technology Aug 2013 - Apr 2017
Design Engineer Ibm Apr 1996 - Jul 2013
Engineer Biotek Instruments May 1985 - Apr 1996
Engineer Hfc Semiconductor Corp May 1985 - Apr 1996
Memory Manage
Education:
University of Vermont 1998 - 2000
Master of Science, Masters, Engineering Castleton University 1987 - 1990
Bachelors, Mathematics, Biology, Chemistry Vermont Technical College 1982 - 1985
Associates, Engineering
Skills:
Asic, Eda, Simulations, Cmos, Vlsi, Physical Design, Circuit Design, Static Timing Analysis, Semiconductors, Spice, Hardware Architecture, Cadence Virtuoso, Functional Verification, Ic, Tcl, Rtl Design, Mixed Signal, Soc, Processors, Analog Circuit Design, Electrical Engineering, Testing, Analog, Embedded Systems, System Architecture, Lvs, Perl, Vhdl, Logic Design, Integrated Circuit Design, Fpga, Verilog, Ddr, Linux, Microprocessors, Timing Closure, Computer Architecture, Firmware, Pcb Design, Algorithms, Team Leadership, Process Improvement, Cadence, Perl Script, Dft, Leading Change, Verilog Ams, Unix, Microelectronics, Synopsis

Publications & IP owners

Us Patents

Method Of Improving Fuse State Detection And Yield In Semiconductor Applications

US Patent:
7403061, Jul 22, 2008
Filed:
Mar 23, 2006
Appl. No.:
11/277315
Inventors:
John E. Barwin - Essex Junction VT, US
Steven H. Lamphier - Colchester VT, US
Harold Pilo - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01H 37/76
US Classification:
327525, 327526, 3652257
Abstract:
Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Fully Synchronous Dll With Architected Update Window

US Patent:
7492199, Feb 17, 2009
Filed:
Jul 28, 2006
Appl. No.:
11/460638
Inventors:
John E. Barwin - Essex Junction VT, US
Harold Pilo - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03L 7/06
US Classification:
327158
Abstract:
The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.

Method Of Managing Electro Migration In Logic Designs And Design Structure Thereof

US Patent:
8560990, Oct 15, 2013
Filed:
Jan 13, 2010
Appl. No.:
12/686457
Inventors:
John E. Barwin - Essex Junction VT, US
Jeanne P. S. Bickford - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716111, 716110
Abstract:
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

Precharging The Write Path Of An Mram Device For Fast Write Operation

US Patent:
2005015, Jul 21, 2005
Filed:
Jan 15, 2004
Appl. No.:
10/758449
Inventors:
Stefan Lammers - South Burlington VT, US
Hans-Heinrich Viehmann - South Burlington VT, US
Thomas Maffitt - Burlington VT, US
John Barwin - Jeffersonville VT, US
International Classification:
G11C011/15
US Classification:
365173000
Abstract:
The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.

Method Of Improving Fuse State Detection And Yield In Semiconductor Applications

US Patent:
2008026, Oct 30, 2008
Filed:
Jun 6, 2008
Appl. No.:
12/134260
Inventors:
John E. Barwin - Essex Junction VT, US
Steven H. Lamphier - Colchester VT, US
Harold Pilo - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01H 37/76
US Classification:
327525
Abstract:
Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Structure For Improving Fuse State Detection And Yield In Semiconductor Applications

US Patent:
2009015, Jun 18, 2009
Filed:
Dec 18, 2007
Appl. No.:
11/958598
Inventors:
John E. Barwin - Essex Junction VT, US
Steven H. Lamphier - Colchester VT, US
Harold Pilo - Underhill VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
H01H 37/76
G06F 17/50
US Classification:
327525, 716 1
Abstract:
Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Design System And Method That, During Timing Analysis, Compensates For Regional Timing Variations

US Patent:
2011010, May 5, 2011
Filed:
Nov 5, 2009
Appl. No.:
12/612909
Inventors:
John E. Barwin - Essex Junction VT, US
Nazmul Habib - South Burlington VT, US
Manikandan Viswanath - South Burlington VT, US
Assignee:
International Business Machines Corporation - Amonk NY
International Classification:
G06F 17/50
US Classification:
716134, 716108, 716118, 716126
Abstract:
Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths.

Integrated Circuit Design Method And System

US Patent:
2013018, Jul 18, 2013
Filed:
Jan 12, 2012
Appl. No.:
13/348850
Inventors:
John E. Barwin - Essex Junction VT, US
Amol A. Joshi - Essex Junction VT, US
Baozhen Li - South Burlington VT, US
Michael R. Ouellette - Westford VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716104
Abstract:
Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

Possible Relatives

Boyd A Barwin  John M Johnson  John Stamps  John R Stan  John Stanard  John R Stanaway  John R Stanbery  John L Stanbrough  John C Stanchak  John Stanchek 

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