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John EitrheimAustin, TX

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Austin, TX   

1642 Hilton Head Ln, Frisco, TX 75034    972-6681847    972-6681852    972-6681863   

2316 Penton Way, Little Elm, TX 75068    972-6681863   

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John Eitrheim

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Work

Company: Formulawise, inc Jul 2011 Position: President & ceo

Education

School / High School: University of Minnesota- Minneapolis, MN 1981 Specialities: BSEE

Skills

High speed logic design • speed improvement • cell placement and layout • SRAM design • clock tree design • circuit design and formal verification.

Industries

Computer Hardware
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John Eitrheim resumes & CV records

Resumes

John Eitrheim Photo 9

Physical Design Engineer

Location:
Austin, TX
Industry:
Computer Hardware
Work:
Formulawise Oct 2011 - Mar 2014
Chief Executive Officer Oracle Oct 2011 - Mar 2014
Senior Principal Hardware Engineer Cisco Jun 2002 - Jul 2011
Senior Design Engineer Navarro Networks Mar 2000 - Jun 2002
Senior Design Engineer Cyrix Corporation Jul 1988 - Mar 2000
Senior Design Engineer Motorola Jul 1981 - Jul 1988
Senior Design Engineer Jul 1981 - Jul 1988
Physical Design Engineer
Education:
University of Minnesota
Bachelors, Electrical Engineering
Skills:
Microprocessors, Soc, Static Timing Analysis, Speed Improvement, Sram Memory Design, Datapath Design, Custom Circuit Design, Clock Tree Design, Lec, Lvs/Drc, Ir Drop, Cadence Tools, Hspice, Primetime, Scripting, Spice, Hardware Architecture, Vlsi, Timing Closure, Semiconductors, Application Specific Integrated Circuits, Circuit Design, Debugging, Embedded Systems, Eda, Processors, Verilog
John Eitrheim Photo 10

John Eitrheim - Frisco, TX

Work:
Formulawise, Inc Jul 2011 to 2000
President & CEO Cisco Systems, Inc - Richardson, TX Jun 2002 to Jul 2011
Senior Design Engineer Navarro Networks - Plano, TX Mar 2000 to Jun 2002
Senior Design Engineer Cyrix Corporation - Richardson, TX Jul 1988 to Mar 2000
Senior Design Engineer Motorola, Inc - Austin, TX Jul 1981 to Jul 1988
Senior Design Engineer
Education:
University of Minnesota - Minneapolis, MN 1981
BSEE
Skills:
High speed logic design, speed improvement, cell placement and layout, SRAM design, clock tree design, circuit design and formal verification.

Publications & IP owners

Us Patents

System And Method For Processing Data In A Memory Array

US Patent:
6788585, Sep 7, 2004
Filed:
Nov 27, 2002
Appl. No.:
10/306281
Inventors:
John K. Eitrheim - Plano TX
Jeffrey A. Huxel - Plano TX
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G11C 1604
US Classification:
36518904, 36518901
Abstract:
A method for processing data is provided that includes receiving a first request in a first clock cycle from a processor for access to a first data segment corresponding to a first address included in the first request. A second request for access to a second data segment corresponding to a second address included in the second request is received during a second clock cycle. The second data segment is disabled from being communicated to the processor and the first data segment is communicated to the processor in response to the second request.

Testing Self-Repairing Memory Of A Device

US Patent:
7007211, Feb 28, 2006
Filed:
Oct 4, 2002
Appl. No.:
10/264551
Inventors:
Christopher E. White - Plano TX, US
Steven C. McMahan - Richardson TX, US
John K. Eitrheim - Plano TX, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G11C 29/00
US Classification:
714718, 714733, 714 30
Abstract:
Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Testing Self-Repairing Memory Of A Device

US Patent:
7490276, Feb 10, 2009
Filed:
Oct 20, 2005
Appl. No.:
11/255383
Inventors:
Christopher E. White - Plano TX, US
Steven C. McMahan - Richardson TX, US
John K. Eitrheim - Plano TX, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G01C 29/00
G01R 31/28
US Classification:
714718, 714733, 714734
Abstract:
Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Transportable Feeding System For Infants And The Like

US Patent:
2007022, Sep 27, 2007
Filed:
Mar 24, 2006
Appl. No.:
11/277378
Inventors:
John Eitrheim - Plano TX, US
Aleene Cooper - Richardson TX, US
Tracy Escobar - Midlothian TX, US
International Classification:
B65D 1/04
US Classification:
215006000
Abstract:
A transportable feeding system for infants and the like comprises an hollow upper chamber for receiving a quantity of powdered food material and a hollow lower chamber for receiving a quantity of water. A normally closed valve member is selectively openable to permit water to flow from the hollow lower chamber into the hollow upper chamber for mixing and feeding.

Single Delay Line Adjustable Duty Cycle Clock Generator

US Patent:
5550499, Aug 27, 1996
Filed:
Apr 18, 1995
Appl. No.:
8/423199
Inventors:
John K. Eitrheim - Plano TX
Assignee:
Cyrix Corporation - Richardson TX
International Classification:
H03K 504
US Classification:
327175
Abstract:
An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal.

Series Read-Only-Memory Having Capacitive Bootstrap Precharging Circuitry

US Patent:
4570239, Feb 11, 1986
Filed:
Jan 24, 1983
Appl. No.:
6/460335
Inventors:
Ernest A. Carter - Austin TX
John K. Eitrheim - Austin TX
Dorothy M. Wood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 1140
G11C 1700
US Classification:
365203
Abstract:
A read-only-memory (ROM) having a plurality of enhancement and depletion transistors selectively arranged in an array with the gates of the transistors in each row connected in common to form word lines, and the current paths of the transistors in each column connected in series to form bit lines. The word lines are precharged and then allowed to float. The bit lines are then precharged, bootstrapping the word lines above the precharge level. A selected one of the word lines is thereafter discharged before one end of each of the bit lines is connected to ground. A selected bit line will either remain precharged or be discharged depending upon the type of transistor at the intersection of the selected word and bit lines.

High Speed Processor For Operation At Reduced Operating Voltage

US Patent:
5878269, Mar 2, 1999
Filed:
Mar 27, 1992
Appl. No.:
7/859347
Inventors:
John K. Eitrheim - Garland TX
Richard B. Reis - Garland TX
Steve McMahan - Richardson TX
Lawrence H. Hudepohl - Richardson TX
Douglas Ewing Duschatko - Plano TX
Tai Dinh Ngo - Arlington TX
Jeffrey Byrne - Garland TX
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
39580042
Abstract:
A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2. 7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5. 5 volts and 40 MHz.

Clock Multiplication Circuit And Method

US Patent:
5359232, Oct 25, 1994
Filed:
Nov 13, 1992
Appl. No.:
7/975809
Inventors:
John K. Eitrheim - Garland TX
Richard B. Reis - McKinney TX
Assignee:
Cyrix Corporation - Richardson TX
International Classification:
H03K 501
US Classification:
307268
Abstract:
An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Possible Relatives

Norman D Eitrheim  John M Johnson  John Stamps  John R Stan  John Stanard  John R Stanaway  John R Stanbery  John L Stanbrough  John C Stanchak  John Stanchek 

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