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John P Guadagna, 8311847 Oak Run Rd, Oak Run, CA 96069

John Guadagna Phones & Addresses

11847 Oak Run Rd, Oak Run, CA 96069    530-5477228   

Valencia, CA   

Dunsmuir, CA   

Weed, CA   

Los Gatos, CA   

Morgan Hill, CA   

Hillsboro, OR   

San Jose, CA   

Mentions for John P Guadagna

Publications & IP owners

Us Patents

Charge Cancelling Structure And Method For Integrated Circuits

US Patent:
3983414, Sep 28, 1976
Filed:
Feb 10, 1975
Appl. No.:
5/548302
Inventors:
Kenneth R. Stafford - San Jose CA
John P. Guadagna - San Jose CA
Assignee:
Fairchild Camera and Instrument Corporation - Mountain View CA
International Classification:
H03K 1716
H03K 1760
US Classification:
307251
Abstract:
According to the invention, the electrical charge which is transferred to a circuit node by the switching ON or OFF of a field effect transistor whose source or drain is connected to that node is cancelled by connecting the source and drain of another field effect transistor to that circuit node and applying to its gate terminal a complement of the switching signal applied to the gate electrode of the first field effect transistor.

Balanced Differential Capacitively Decoupled Charge Sensor

US Patent:
3983413, Sep 28, 1976
Filed:
May 2, 1975
Appl. No.:
5/574185
Inventors:
Kamleshwar C. Gunsagar - Campbell CA
John P. Guadagna - San Jose CA
Assignee:
Fairchild Camera and Instrument Corporation - Mountain View CA
International Classification:
H03K 520
H01L 2978
G11C 1928
US Classification:
307235F
Abstract:
A balanced differential capacitively decoupled charge sensor for detecting small amounts of charge comprises balanced differential sensing means adapted to receive charge representing data and charge representing a reference value, a pair of capacitance decoupling transistors, the respective drains of each of said pair of capacitance decoupling transistors being electrically coupled to the respective inputs of said differential sensing means, a matched pair of charge output nodes electrically coupled to the respective sources of said capacitance decoupling transistors and adapted to receive, respectively, data charge and reference charge, and means for biasing and resetting both of said charge output nodes so that said capacitance decoupling transistors are functioning in a high transconductance mode when data charge and reference charge are received.

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