BackgroundCheck.run
Search For

John M Kessenich, 621200 43Rd Ave UNIT 18, Greeley, CO 80634

Known as:
John Michael Kessenich John E Kessenich Jhon M Kessenich John M Kessenic Essenice K John
Related to:
Debra L Yi 71

John Kessenich Phones & Addresses

Greeley, CO   

210 Magnolia St, Fort Collins, CO 80521    970-4849961   

210 W Magnolia St #340, Fort Collins, CO 80521    970-4849961   

507 Skysail Ln, Fort Collins, CO 80525    970-2265258   

640 Peterson St, Fort Collins, CO 80524    970-4849961   

Social networks

John M Kessenich

Linkedin

Work

Company: Lunarg Sep 2010 Position: Senior compiler architect

Education

Degree: MS School / High School: Colorado State University 1981 to 1988 Specialities: Mathematics

Skills

C++ • C • Compilers • Object Oriented Design • Software Engineering • Gpu • Computer Graphics • Architecture • Programming • Oop • Opengl • Device Drivers • Glsl • Shaders • Computer Architecture • Software Development • High Performance Computing • Embedded Systems • Debugging • Multithreading

Industries

Computer Software
Get Report
Control this profile

Mentions for John M Kessenich

John Kessenich resumes & CV records

Resumes

John Kessenich Photo 12

Spir-V Specification Author And Editor

Location:
941 Lincoln Ave, Steamboat Springs, CO 80487
Industry:
Computer Software
Work:
LunarG since Sep 2010
Senior Compiler Architect Khronos Group since Jan 2004
Specification Editor OpenGL Shading Language Intel Apr 2006 - Sep 2010
Senior Staff Architect 3Dlabs 1999 - 2006
Senior Engineer Hewlett-Packard 1985 - 1999
Member of Technical Staff
Education:
Colorado State University 1981 - 1988
MS, Mathematics
Skills:
C++, C, Compilers, Object Oriented Design, Software Engineering, Gpu, Computer Graphics, Architecture, Programming, Oop, Opengl, Device Drivers, Glsl, Shaders, Computer Architecture, Software Development, High Performance Computing, Embedded Systems, Debugging, Multithreading

Publications & IP owners

Us Patents

Apparatus And Method For A Virtual Hashed Page Table

US Patent:
6430670, Aug 6, 2002
Filed:
Nov 1, 2000
Appl. No.:
09/703536
Inventors:
William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
John M. Kessenich - Fort Collins CO
Jonathan K. Ross - Sunnyvale CA
Gary N. Hammond - Campbell CA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA
Assignee:
Hewlett-Packard Co. - Palo Alto CA
International Classification:
G06F 1200
US Classification:
711216, 711205, 711206
Abstract:
The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

System And Method For Monitoring Unaligned Memory Accesses

US Patent:
6772372, Aug 3, 2004
Filed:
Mar 6, 2001
Appl. No.:
09/800283
Inventors:
Bret A. McKee - Fort Collins CO
John M. Kessenich - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714 42, 712244
Abstract:
A system monitors unaligned memory accesses by a processor of a computer system. The processor automatically generates a fault when attempting an unaligned memory access. Unaligned memory access faults are disabled in response to a fault generated by a first faulting instruction. The first faulting instruction is executed. A trap is generated by executing the first faulting instruction. Unaligned memory access faults are enabled in response to the trap.

Apparatus And Method For A Virtual Hashed Page Table

US Patent:
6216214, Apr 10, 2001
Filed:
Feb 3, 1998
Appl. No.:
9/018326
Inventors:
William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
John M. Kessenich - Fort Collins CO
Jonathan K. Ross - Sunnyvale CA
Gary N. Hammond - Campbell CA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA
Assignee:
Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA
International Classification:
G06F 1210
US Classification:
711207
Abstract:
The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

Isbn (Books And Publications)

Opengl Shading Language

Author:
John M. Kessenich
ISBN #:
0321197895

Opengl Shading Language

Author:
John M. Kessenich
ISBN #:
0321334892

Possible Relatives

Joseph M Kessenich  Mary E Kessenich  Paul D Kessenich  Roger A Kessenich  Wes R Kessenich  William H Kessenich  Beth R Kessenich  John M Johnson  John Stamps  John R Stan 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.