John Chih Chieh Lin, 51380 Jordan Ave, Clovis, CA 93611

6650880, Nov 18, 2003

Jun 12, 2000

09/593583

Sherman Lee - Rancho Palos Verdes CA
Vivian Y. Chou - Alhambra CA
John H. Lin - Downey CA

Broadcom Corporation - Irvine CA

H04B 106

455259, 455 41, 455265, 375372

A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e. g. , including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver. A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system.

6804772, Oct 12, 2004

Mar 21, 2001

09/815098

Sherman Lee - Rancho Palos Verdes CA
Vivian Y. Chou - Alhambra CA
John H. Lin - Downey CA

Broadcom Corporation - Irvine CA

G06F 1202

712248, 711149, 711152

A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

D518030, Mar 28, 2006

Jun 14, 2004

29/207558

John Lin - Pacific Palisades CA, US

Ten Ventures Inc. - Pacific Palisades CA

1403

D14218

7123877, Oct 17, 2006

Nov 8, 2001

10/007435

John Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 7/00
H04Q 7/20

455 412, 455507, 455514, 455517

A baseband controller includes a microsequencer that is formed to include special hardware resources and a configuration that facilitates using the micro-sequencer as a real-time baseband controller. The microsequencer includes a 72-bit correlator that way also be used as an accumulator. The correlator is able to communicate with a 72-bit arithmetic logic unit, enabling the correlator to act as an accumulator, as well as a plurality of clocks and timers that facilitate the timing functionality to satisfy Bluetooth specifications. More specifically, the microsequencer includes at least four clocks and eight times. The four clocks include an externally driven Bluetooth clock, an externally driven real-time clock, a native Bluetooth clock and a native real-time clock. The microsequencer further includes at least four registers for temporarily storing computational data. The storage registers have different sizes for storing different sized packets of computational data.

7151745, Dec 19, 2006

Nov 8, 2001

10/008873

John Lin - Downey CA, US
Paris Chen - Walnut CA, US

Broadcom Corporation - Irvine CA

H04J 1/16
H04J 3/14

370230, 370235

A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event. One aspect is to avoid a possibility of collision between synchronized and non-synchronized communication events. The schedule of synchronized events are evaluated in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision. The transmission determination includes evaluating future time periods to see if a synchronized event is scheduled during a time period in which the non-synchronized event would continue to be transmitted for those non-synchronized events that span two or more defined time periods in length.

D534896, Jan 9, 2007

Jun 14, 2004

29/207551

John Lin - Pacific Palisades CA, US

Ten Ventures Inc. - Pacific Palisades CA

1403

D14188

7167727, Jan 23, 2007

Sep 30, 2003

10/674693

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 1/38

455557, 455 412, 455259, 455265

A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e. g. , including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver. A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system.

7228392, Jun 5, 2007

Apr 15, 2003

10/413689

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

G06F 12/02

711154

A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.