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John F Mcintee, 686672 Hacienda La Noria Ln, Apache Junction, AZ 85217

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6672 Hacienda La Noria Ln, Apache Junction, AZ 85217   

Gold Canyon, AZ   

Superior, AZ   

4703 Holston River Ct, San Jose, CA 95136   

Santa Clara, CA   

New York, NY   

Pinedale, AZ   

New City, NY   

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Us Patents

Apparatus And Methods For Manipulating Semiconductor Wafers

US Patent:
6869266, Mar 22, 2005
Filed:
Jun 5, 2003
Appl. No.:
10/455534
Inventors:
Stephen D. Coomer - Tempe AZ, US
John Francis McIntee - Gold Canyon AZ, US
Jozsef Michael Iha - Gold Canyon AZ, US
Robert T. Borra - Austin TX, US
Eric Lusby - Mesa AZ, US
Michael J. Lombardi - Phoenix AZ, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
B25J015/06
US Classification:
414627, 414806, 414941
Abstract:
Apparatus and methods for a wafer handling system that manipulates semiconductor wafers. The invention includes an end effector having a vacuum chuck, an internal vacuum plenum, and flow diverters positioned within the vacuum plenum that define vacuum distribution channels coupled in fluid communication with vacuum ports of the vacuum chuck. The invention also includes a vacuum chuck having flow diverters positioned in one or more internal vacuum plenums that are in fluid communication with the vacuum ports of the vacuum chuck. The flow diverters adjust the vacuum pressure supplied to the vacuum ports such that, as vacuum ports are occluded by the wafer, the vacuum pressure is preferentially applied to unblocked vacuum ports for increasing the attractive force applied to unengaged portions of the wafer. The apparatus of the present invention has particularly utility for securing thin semiconductor wafers with a significant warpage.

Sputtering Cathode Adapter Assembly And Method

US Patent:
6998033, Feb 14, 2006
Filed:
May 14, 2003
Appl. No.:
10/438304
Inventors:
John Lawson - Chandler AZ, US
Dale Irwin - Mesa AZ, US
Steve Chervenak - Phoenix AZ, US
John McIntee - Gold Canyon AZ, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
C23C 14/34
US Classification:
20429811, 2041921, 20419212
Abstract:
An adapter assembly is provided for supporting a sputtering cathode in a fixed opening in the chamber of a sputter coating machine. The assembly includes: one of several adapter bodies, each configured to support, in the fixed opening, a target of one of a plurality of sizes and types, and at one of several target-to-substrate spacings; one of several insulator rings, each for a target of a different size or type; one of several dark-space shields, each for a target of a different size, type, material, or processing pressure; and one of several adapter shields, each for a different adapter body and target material. Only the shields accumulate deposits and require cleaning or replacement. The dark-space shield is spaced from the target rim by a gap of at 0. 045 to 0. 067 inches to form a deep narrow space that prevents deposits onto the insulator ring while avoiding arcing and plasma formation in the gap. A method is provided for existing sputtering machines with the assembly, which accommodates different targets and processes.

Sputtering Cathode Adapter Assembly And Method

US Patent:
2006003, Feb 16, 2006
Filed:
Oct 21, 2005
Appl. No.:
11/255825
Inventors:
John Lawson - Chandler AZ, US
Dale Irwin - Mesa AZ, US
Steve Chervenak - Phoenix AZ, US
John McIntee - Gold Canyon AZ, US
International Classification:
C23C 14/35
US Classification:
204298120, 204298190
Abstract:
An adapter assembly is provided for supporting a sputtering cathode in a fixed opening in the chamber of a sputter coating machine. The assembly includes: one of several adapter bodies, each configured to support, in the fixed opening, a target of one of a plurality of sizes and types, and at one of several target-to-substrate spacings; one of several insulator rings, each for a target of a different size or type; one of several dark-space shields, each for a target of a different size, type, material, or processing pressure; and one of several adapter shields, each for a different adapter body and target material. Only the shields accumulate deposits and require cleaning or replacement. The dark-space shield is spaced from the target rim by a gap of at 0.045 to 0.067 inches to form a deep narrow space that prevents deposits onto the insulator ring while avoiding arcing and plasma formation in the gap. A method is provided for existing sputtering machines with the assembly, which accommodates different targets and processes.

Apparatus And Methods For Manipulating Semiconductor Wafers

US Patent:
6612590, Sep 2, 2003
Filed:
Jan 12, 2001
Appl. No.:
09/759613
Inventors:
Stephen D. Coomer - Tempe AZ
John Francis McIntee - Gold Canyon AZ
Jozsef Michael Iha - Gold Canyon AZ
Robert T. Borra - Austin TX
Eric Lusby - Mesa AZ
Michael J. Lombardi - Phoenix AZ
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
B65G 4724
US Classification:
279158, 414806, 414755
Abstract:
Apparatus and methods for a wafer handling system that manipulates semiconductor wafers. The present invention includes an end effector having a vacuum chuck, an internal vacuum plenum, and a plurality of flow diverters positioned within the vacuum plenum to define vacuum distribution channels in fluid communication with respective vacuum ports of the vacuum chuck. The present invention also includes a vacuum chuck having flow diverters positioned in one or more internal vacuum plenums which are in fluid communication with the vacuum ports of the vacuum chuck. The flow diverters of the vacuum chucks adjust the vacuum pressure supplied to the vacuum ports such that, as vacuum ports are occluded by the wafer, the vacuum pressure is preferentially applied to unblocked vacuum ports for increasing the attractive force applied to unengaged portions of the wafer. The wafer handling system also includes a gas dispensing showerhead that may be positioned above a vacuum chuck for flattening the wafer so that a vacuum chuck can establish a secure engagement. The apparatus of the present invention has particularly utility for securing thin semiconductor wafers with a significant warpage.

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