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John G Olenick, 8938586 Yolanda St, Selbyville, DE 19975

John Olenick Phones & Addresses

38586 Yolanda St, Selbyville, DE 19975    302-4365510   

9 Yolanda St, Selbyville, DE 19975    302-4365510   

7206 Carriage Hill Dr, Laurel, MD 20707    301-7761382   

Burtonsville, MD   

Rome, GA   

38586 Yolanda St, Selbyville, DE 19975    301-6514326   

Work

Position: Installation, Maintenance, and Repair Occupations

Education

Degree: Associate degree or higher

Emails

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Career records & work history

License Records

John R. Olenick

Licenses:
License #: T1-0004899 - Expired
Category: Electrical Examiners
Type: Master Electrician

John Olenick resumes & CV records

Resumes

John Olenick Photo 22

John Olenick

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John Olenick

Publications & IP owners

Us Patents

Cavity-Down Chip Carrier With Pad Grid Array

US Patent:
5027191, Jun 25, 1991
Filed:
May 11, 1989
Appl. No.:
7/350872
Inventors:
Robert A. Bourdelaise - Crofton MD
David B. Harris - Columbia MD
Denise B. Harris - Columbia MD
John A. Olenick - Columbia MD
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 2312
H01L 2302
US Classification:
357 74
Abstract:
The invention is an improved chip carrier assembly utilizing a cavity-down chip carrier with a pad grid array wherein the IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip carrier is attached such that heat transfer from the IC chip may occur along a short path to a heat sink such that a large heat transfer rate is possible. Furthermore, the apparatus utilizes an alignment and electrical connection means between the contact pads of the chip carrier and a PWB to which the chip carrier is attached to compensate for shrinkage variation which occurs during the chip carrier fabrication process. Furthermore, within the cavity of the chip carrier there is space for additional components such as a decoupling capacitors. This permits the design of an apparatus providing better heat transfer properties, more accurate contact pad locations and the option of including within the chip carrier components which in the past had been mounted outside of the chip carrier.

Float Device For Density Gradient Fractionation

US Patent:
4346608, Aug 31, 1982
Filed:
Jul 31, 1980
Appl. No.:
6/174069
Inventors:
John G. Olenick - Laurel MD
Patrick E. Lorenz - Olney MD
Assignee:
The United States of America as represented by the Secretary of the Army - Washington DC
International Classification:
G01N 114
US Classification:
7386321
Abstract:
A float device is provided for density gradient fractionation which permits continuous removal of liquid samples from the surface of the liquid within a tube. The float device floats on the liquid surface and is provided with a centrally disposed length of tubing which extends through the device to provide communication between the liquid surface and a suction source such as a peristaltic pump. A concavity in the bottom of the float assists in removing trapped air and minimizes turbulent flow, thereby assuring high resolution of obtained samples.

Co-Fired Ceramic Package For A Power Circuit

US Patent:
5041695, Aug 20, 1991
Filed:
Jun 1, 1989
Appl. No.:
7/360071
Inventors:
John A. Olenick - Columbia MD
Allen B. Timberlake - Columbia MD
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 2302
H05K 506
US Classification:
174 524
Abstract:
Both a co-fired ceramic package for a power circuit is disclosed as well as a method of manufacture thereof. The package includes a base which is formed from a plurality of pyrolizable ceramic films, each of which includes a heat-conductive and electrically insulative ceramic material such as aluminum nitride, silicon carbide or beryllium oxide embedded within a binder. In the method of the invention, two or three ceramic films are metalized with a pattern of conductive material on their top surfaces. The resulting metalized films are then stacked over a plurality of unmetalized ceramic films, and the resulting aggregate stack is laminated together by the application of heat and pressure. Electrical components are then soldered onto the top surface of the base, and a cover is sealingly connected around the resulting hybrid circuit. The metalization step advantageously forms terminals around the cover which allow access to the heat generating power circuit without the need for glass post seals.

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